
/*
$Id: ddr23.h,v 1.3.198.1 Broadcom SDK $
$Copyright: Copyright 2011 Broadcom Corporation.
This program is the proprietary software of Broadcom Corporation
and/or its licensors, and may only be used, duplicated, modified
or distributed pursuant to the terms and conditions of a separate,
written license agreement executed between you and Broadcom
(an "Authorized License").  Except as set forth in an Authorized
License, Broadcom grants no license (express or implied), right
to use, or waiver of any kind with respect to the Software, and
Broadcom expressly reserves all rights in and to the Software
and all intellectual property rights therein.  IF YOU HAVE
NO AUTHORIZED LICENSE, THEN YOU HAVE NO RIGHT TO USE THIS SOFTWARE
IN ANY WAY, AND SHOULD IMMEDIATELY NOTIFY BROADCOM AND DISCONTINUE
ALL USE OF THE SOFTWARE.  
 
Except as expressly set forth in the Authorized License,
 
1.     This program, including its structure, sequence and organization,
constitutes the valuable trade secrets of Broadcom, and you shall use
all reasonable efforts to protect the confidentiality thereof,
and to use this information only in connection with your use of
Broadcom integrated circuit products.
 
2.     TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS
PROVIDED "AS IS" AND WITH ALL FAULTS AND BROADCOM MAKES NO PROMISES,
REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY,
OR OTHERWISE, WITH RESPECT TO THE SOFTWARE.  BROADCOM SPECIFICALLY
DISCLAIMS ANY AND ALL IMPLIED WARRANTIES OF TITLE, MERCHANTABILITY,
NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES,
ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
CORRESPONDENCE TO DESCRIPTION. YOU ASSUME THE ENTIRE RISK ARISING
OUT OF USE OR PERFORMANCE OF THE SOFTWARE.

3.     TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL
BROADCOM OR ITS LICENSORS BE LIABLE FOR (i) CONSEQUENTIAL,
INCIDENTAL, SPECIAL, INDIRECT, OR EXEMPLARY DAMAGES WHATSOEVER
ARISING OUT OF OR IN ANY WAY RELATING TO YOUR USE OF OR INABILITY
TO USE THE SOFTWARE EVEN IF BROADCOM HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES; OR (ii) ANY AMOUNT IN EXCESS OF
THE AMOUNT ACTUALLY PAID FOR THE SOFTWARE ITSELF OR USD 1.00,
WHICHEVER IS GREATER. THESE LIMITATIONS SHALL APPLY NOTWITHSTANDING
ANY FAILURE OF ESSENTIAL PURPOSE OF ANY LIMITED REMEDY.$
*/

/***************************************************************************
 *     Copyright (c) 1999-2009, Broadcom Corporation
 *     All Rights Reserved
 *     Confidential Property of Broadcom Corporation
 *
 *
 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
 * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
 *
 * $brcm_Workfile: $
 * $brcm_Revision: $
 * $brcm_Date: $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Wed Jan 21 14:22:25 2009
 *                 MD5 Checksum         f9d424ae6d1d678638d610ed40ca6807
 *
 * Compiled with:  RDB Utility          5.0
 *                 RDB Parser           3.0
 *                 rdb2macro.pm         4.0
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Spec Versions:  DDR23_PHY_ADDR_CTL   1
 *                 DDR23_PHY_BYTE_LANE  04
 *
 * RDB Files:  /projects/ntsw-sw/home/zhongx/views/system_sim_ss_bringup/sdk/src/soc/phy/regs/ddr23/ddr23.rdb
 *             /projects/ntsw-sw/home/zhongx/views/system_sim_ss_bringup/sdk/src/soc/phy/regs/ddr23/ddr23_phy_addr_ctl.rdb
 *             /projects/ntsw-sw/home/zhongx/views/system_sim_ss_bringup/sdk/src/soc/phy/regs/ddr23/ddr23_phy_byte_lane.rdb
 *
 * Revision History:
 *
 * $brcm_Log: $
 *
 ***************************************************************************/

#ifndef DDR23_H__
#define DDR23_H__

/**
 * m = memory, c = core, r = register, f = field, d = data.
 */
#if !defined(GET_FIELD) && !defined(SET_FIELD)
#define BRCM_ALIGN(c,r,f)   c##_##r##_##f##_ALIGN
#define BRCM_BITS(c,r,f)    c##_##r##_##f##_BITS
#define BRCM_MASK(c,r,f)    c##_##r##_##f##_MASK
#define BRCM_SHIFT(c,r,f)   c##_##r##_##f##_SHIFT

#define GET_FIELD(m,c,r,f) \
	((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f))

#define SET_FIELD(m,c,r,f,d) \
	((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \
	 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \
	)

#define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d)
#define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d)
#define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d)

#endif /* GET & SET */

/****************************************************************************
 * Core Enums.
 ***************************************************************************/
/****************************************************************************
 * DDR23_PHY_DDR23_PHY_ADDR_CTL
 ***************************************************************************/

/* Address & Control revision register */
#define READ_DDR23_PHY_ADDR_CTL_REVISIONr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000000, (_val))
#define WRITE_DDR23_PHY_ADDR_CTL_REVISIONr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000000, (_val))
#define MODIFY_DDR23_PHY_ADDR_CTL_REVISIONr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000000, (_val), (_mask))

/* PHY clock power management control register */
#define READ_DDR23_PHY_ADDR_CTL_CLK_PM_CTRLr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000004, (_val))
#define WRITE_DDR23_PHY_ADDR_CTL_CLK_PM_CTRLr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000004, (_val))
#define MODIFY_DDR23_PHY_ADDR_CTL_CLK_PM_CTRLr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000004, (_val), (_mask))

/* PHY PLL status register */
#define READ_DDR23_PHY_ADDR_CTL_PLL_STATUSr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000010, (_val))
#define WRITE_DDR23_PHY_ADDR_CTL_PLL_STATUSr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000010, (_val))
#define MODIFY_DDR23_PHY_ADDR_CTL_PLL_STATUSr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000010, (_val), (_mask))

/* PHY PLL configuration register */
#define READ_DDR23_PHY_ADDR_CTL_PLL_CONFIGr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000014, (_val))
#define WRITE_DDR23_PHY_ADDR_CTL_PLL_CONFIGr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000014, (_val))
#define MODIFY_DDR23_PHY_ADDR_CTL_PLL_CONFIGr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000014, (_val), (_mask))

/* PHY PLL pre-divider control register */
#define READ_DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDERr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000018, (_val))
#define WRITE_DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDERr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000018, (_val))
#define MODIFY_DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDERr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000018, (_val), (_mask))

/* PHY PLL divider control register */
#define READ_DDR23_PHY_ADDR_CTL_PLL_DIVIDERr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x0000001c, (_val))
#define WRITE_DDR23_PHY_ADDR_CTL_PLL_DIVIDERr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x0000001c, (_val))
#define MODIFY_DDR23_PHY_ADDR_CTL_PLL_DIVIDERr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x0000001c, (_val), (_mask))

/* PHY PLL analog control register #1 */
#define READ_DDR23_PHY_ADDR_CTL_PLL_CONTROL1r(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000020, (_val))
#define WRITE_DDR23_PHY_ADDR_CTL_PLL_CONTROL1r(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000020, (_val))
#define MODIFY_DDR23_PHY_ADDR_CTL_PLL_CONTROL1r(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000020, (_val), (_mask))

/* PHY PLL analog control register #2 */
#define READ_DDR23_PHY_ADDR_CTL_PLL_CONTROL2r(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000024, (_val))
#define WRITE_DDR23_PHY_ADDR_CTL_PLL_CONTROL2r(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000024, (_val))
#define MODIFY_DDR23_PHY_ADDR_CTL_PLL_CONTROL2r(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000024, (_val), (_mask))

/* PHY PLL spread spectrum config register */
#define READ_DDR23_PHY_ADDR_CTL_PLL_SS_ENr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000028, (_val))
#define WRITE_DDR23_PHY_ADDR_CTL_PLL_SS_ENr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000028, (_val))
#define MODIFY_DDR23_PHY_ADDR_CTL_PLL_SS_ENr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000028, (_val), (_mask))

/* PHY PLL spread spectrum config register */
#define READ_DDR23_PHY_ADDR_CTL_PLL_SS_CFGr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x0000002c, (_val))
#define WRITE_DDR23_PHY_ADDR_CTL_PLL_SS_CFGr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x0000002c, (_val))
#define MODIFY_DDR23_PHY_ADDR_CTL_PLL_SS_CFGr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x0000002c, (_val), (_mask))

/* Address & Control VDL static override control register */
#define READ_DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDEr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000030, (_val))
#define WRITE_DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDEr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000030, (_val))
#define MODIFY_DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDEr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000030, (_val), (_mask))

/* Address & Control VDL dynamic override control register */
#define READ_DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDEr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000034, (_val))
#define WRITE_DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDEr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000034, (_val))
#define MODIFY_DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDEr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000034, (_val), (_mask))

/* Idle mode SSTL pad control register */
#define READ_DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROLr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000038, (_val))
#define WRITE_DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROLr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000038, (_val))
#define MODIFY_DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROLr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000038, (_val), (_mask))

/* PVT Compensation control and status register */
#define READ_DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTLr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x0000003c, (_val))
#define WRITE_DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTLr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x0000003c, (_val))
#define MODIFY_DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTLr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x0000003c, (_val), (_mask))

/* SSTL pad drive characteristics control register */
#define READ_DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTLr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000040, (_val))
#define WRITE_DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTLr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000040, (_val))
#define MODIFY_DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000040, (_val), (_mask))

/* Clock Regulator control register */
#define READ_DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROLr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000044, (_val))
#define WRITE_DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROLr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000044, (_val))
#define MODIFY_DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROLr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000044, (_val), (_mask))


/****************************************************************************
 * DDR23_PHY_DDR23_PHY_BYTE_LANE0
 ***************************************************************************/

/* Byte lane revision register */
#define READ_DDR23_PHY_BYTE_LANE0_REVISIONr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000100, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE0_REVISIONr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000100, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE0_REVISIONr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000100, (_val), (_mask))

/* Byte lane VDL calibration control register */
#define READ_DDR23_PHY_BYTE_LANE0_VDL_CALIBRATEr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000104, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE0_VDL_CALIBRATEr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000104, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE0_VDL_CALIBRATEr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000104, (_val), (_mask))

/* Byte lane VDL calibration status register */
#define READ_DDR23_PHY_BYTE_LANE0_VDL_STATUSr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000108, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE0_VDL_STATUSr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000108, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE0_VDL_STATUSr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000108, (_val), (_mask))

/* Read DQSP VDL static override control register */
#define READ_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0r(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000110, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0r(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000110, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0r(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000110, (_val), (_mask))

/* Read DQSN VDL static override control register */
#define READ_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1r(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000114, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1r(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000114, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1r(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000114, (_val), (_mask))

/* Read Enable VDL static override control register */
#define READ_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2r(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000118, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2r(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000118, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2r(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000118, (_val), (_mask))

/* Write data and mask VDL static override control register */
#define READ_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3r(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x0000011c, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3r(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x0000011c, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3r(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x0000011c, (_val), (_mask))

/* Read DQSP VDL dynamic override control register */
#define READ_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4r(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000120, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4r(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000120, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4r(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000120, (_val), (_mask))

/* Read DQSN VDL dynamic override control register */
#define READ_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5r(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000124, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5r(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000124, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5r(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000124, (_val), (_mask))

/* Read Enable VDL dynamic override control register */
#define READ_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6r(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000128, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6r(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000128, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6r(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000128, (_val), (_mask))

/* Write data and mask VDL dynamic override control register */
#define READ_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7r(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x0000012c, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7r(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x0000012c, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7r(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x0000012c, (_val), (_mask))

/* Byte Lane read channel control register */
#define READ_DDR23_PHY_BYTE_LANE0_READ_CONTROLr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000130, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE0_READ_CONTROLr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000130, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE0_READ_CONTROLr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000130, (_val), (_mask))

/* Read fifo status register */
#define READ_DDR23_PHY_BYTE_LANE0_READ_FIFO_STATUSr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000134, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE0_READ_FIFO_STATUSr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000134, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE0_READ_FIFO_STATUSr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000134, (_val), (_mask))

/* Read fifo status clear register */
#define READ_DDR23_PHY_BYTE_LANE0_READ_FIFO_CLEARr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000138, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE0_READ_FIFO_CLEARr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000138, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE0_READ_FIFO_CLEARr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000138, (_val), (_mask))

/* Idle mode SSTL pad control register */
#define READ_DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROLr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x0000013c, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROLr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x0000013c, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROLr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x0000013c, (_val), (_mask))

/* SSTL pad drive characteristics control register */
#define READ_DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTLr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000140, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTLr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000140, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000140, (_val), (_mask))

/* Clock pad disable register */
#define READ_DDR23_PHY_BYTE_LANE0_CLOCK_PAD_DISABLEr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000144, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE0_CLOCK_PAD_DISABLEr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000144, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE0_CLOCK_PAD_DISABLEr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000144, (_val), (_mask))

/* Write cycle preamble control register */
#define READ_DDR23_PHY_BYTE_LANE0_WR_PREAMBLE_MODEr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000148, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE0_WR_PREAMBLE_MODEr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000148, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE0_WR_PREAMBLE_MODEr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000148, (_val), (_mask))

/* Clock Regulator control register */
#define READ_DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROLr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x0000014c, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROLr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x0000014c, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROLr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x0000014c, (_val), (_mask))


/****************************************************************************
 * DDR23_PHY_DDR23_PHY_BYTE_LANE1
 ***************************************************************************/

/* Byte lane revision register */
#define READ_DDR23_PHY_BYTE_LANE1_REVISIONr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000200, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE1_REVISIONr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000200, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE1_REVISIONr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000200, (_val), (_mask))

/* Byte lane VDL calibration control register */
#define READ_DDR23_PHY_BYTE_LANE1_VDL_CALIBRATEr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000204, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE1_VDL_CALIBRATEr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000204, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE1_VDL_CALIBRATEr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000204, (_val), (_mask))

/* Byte lane VDL calibration status register */
#define READ_DDR23_PHY_BYTE_LANE1_VDL_STATUSr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000208, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE1_VDL_STATUSr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000208, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE1_VDL_STATUSr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000208, (_val), (_mask))

/* Read DQSP VDL static override control register */
#define READ_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0r(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000210, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0r(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000210, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0r(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000210, (_val), (_mask))

/* Read DQSN VDL static override control register */
#define READ_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1r(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000214, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1r(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000214, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1r(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000214, (_val), (_mask))

/* Read Enable VDL static override control register */
#define READ_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2r(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000218, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2r(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000218, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2r(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000218, (_val), (_mask))

/* Write data and mask VDL static override control register */
#define READ_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3r(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x0000021c, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3r(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x0000021c, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3r(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x0000021c, (_val), (_mask))

/* Read DQSP VDL dynamic override control register */
#define READ_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4r(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000220, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4r(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000220, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4r(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000220, (_val), (_mask))

/* Read DQSN VDL dynamic override control register */
#define READ_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5r(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000224, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5r(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000224, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5r(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000224, (_val), (_mask))

/* Read Enable VDL dynamic override control register */
#define READ_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6r(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000228, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6r(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000228, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6r(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000228, (_val), (_mask))

/* Write data and mask VDL dynamic override control register */
#define READ_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7r(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x0000022c, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7r(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x0000022c, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7r(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x0000022c, (_val), (_mask))

/* Byte Lane read channel control register */
#define READ_DDR23_PHY_BYTE_LANE1_READ_CONTROLr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000230, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE1_READ_CONTROLr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000230, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE1_READ_CONTROLr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000230, (_val), (_mask))

/* Read fifo status register */
#define READ_DDR23_PHY_BYTE_LANE1_READ_FIFO_STATUSr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000234, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE1_READ_FIFO_STATUSr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000234, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE1_READ_FIFO_STATUSr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000234, (_val), (_mask))

/* Read fifo status clear register */
#define READ_DDR23_PHY_BYTE_LANE1_READ_FIFO_CLEARr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000238, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE1_READ_FIFO_CLEARr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000238, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE1_READ_FIFO_CLEARr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000238, (_val), (_mask))

/* Idle mode SSTL pad control register */
#define READ_DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROLr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x0000023c, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROLr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x0000023c, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROLr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x0000023c, (_val), (_mask))

/* SSTL pad drive characteristics control register */
#define READ_DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTLr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000240, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTLr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000240, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000240, (_val), (_mask))

/* Clock pad disable register */
#define READ_DDR23_PHY_BYTE_LANE1_CLOCK_PAD_DISABLEr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000244, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE1_CLOCK_PAD_DISABLEr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000244, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE1_CLOCK_PAD_DISABLEr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000244, (_val), (_mask))

/* Write cycle preamble control register */
#define READ_DDR23_PHY_BYTE_LANE1_WR_PREAMBLE_MODEr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000248, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE1_WR_PREAMBLE_MODEr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000248, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE1_WR_PREAMBLE_MODEr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000248, (_val), (_mask))

/* Clock Regulator control register */
#define READ_DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROLr(_unit, _pc, _val) \
             DDR23_REG_READ((_unit), (_pc), 0x00, 0x0000024c, (_val))
#define WRITE_DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROLr(_unit, _pc, _val) \
             DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x0000024c, (_val))
#define MODIFY_DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROLr(_unit, _pc, _val, _mask) \
             DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x0000024c, (_val), (_mask))


/****************************************************************************
 * DDR23_PHY_DDR23_PHY_ADDR_CTL
 ***************************************************************************/
/****************************************************************************
 * DDR23_PHY_ADDR_CTL :: REVISION
 ***************************************************************************/
/* DDR23_PHY_ADDR_CTL :: REVISION :: reserved0 [31:16] */
#define DDR23_PHY_ADDR_CTL_REVISION_RESERVED0_MASK                 0xffff0000
#define DDR23_PHY_ADDR_CTL_REVISION_RESERVED0_ALIGN                0
#define DDR23_PHY_ADDR_CTL_REVISION_RESERVED0_BITS                 16
#define DDR23_PHY_ADDR_CTL_REVISION_RESERVED0_SHIFT                16

/* DDR23_PHY_ADDR_CTL :: REVISION :: MAJOR [15:08] */
#define DDR23_PHY_ADDR_CTL_REVISION_MAJOR_MASK                     0x0000ff00
#define DDR23_PHY_ADDR_CTL_REVISION_MAJOR_ALIGN                    0
#define DDR23_PHY_ADDR_CTL_REVISION_MAJOR_BITS                     8
#define DDR23_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT                    8

/* DDR23_PHY_ADDR_CTL :: REVISION :: MINOR [07:00] */
#define DDR23_PHY_ADDR_CTL_REVISION_MINOR_MASK                     0x000000ff
#define DDR23_PHY_ADDR_CTL_REVISION_MINOR_ALIGN                    0
#define DDR23_PHY_ADDR_CTL_REVISION_MINOR_BITS                     8
#define DDR23_PHY_ADDR_CTL_REVISION_MINOR_SHIFT                    0


/****************************************************************************
 * DDR23_PHY_ADDR_CTL :: CLK_PM_CTRL
 ***************************************************************************/
/* DDR23_PHY_ADDR_CTL :: CLK_PM_CTRL :: reserved0 [31:01] */
#define DDR23_PHY_ADDR_CTL_CLK_PM_CTRL_RESERVED0_MASK              0xfffffffe
#define DDR23_PHY_ADDR_CTL_CLK_PM_CTRL_RESERVED0_ALIGN             0
#define DDR23_PHY_ADDR_CTL_CLK_PM_CTRL_RESERVED0_BITS              31
#define DDR23_PHY_ADDR_CTL_CLK_PM_CTRL_RESERVED0_SHIFT             1

/* DDR23_PHY_ADDR_CTL :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */
#define DDR23_PHY_ADDR_CTL_CLK_PM_CTRL_DIS_DDR_CLK_MASK            0x00000001
#define DDR23_PHY_ADDR_CTL_CLK_PM_CTRL_DIS_DDR_CLK_ALIGN           0
#define DDR23_PHY_ADDR_CTL_CLK_PM_CTRL_DIS_DDR_CLK_BITS            1
#define DDR23_PHY_ADDR_CTL_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT           0


/****************************************************************************
 * DDR23_PHY_ADDR_CTL :: PLL_STATUS
 ***************************************************************************/
/* DDR23_PHY_ADDR_CTL :: PLL_STATUS :: reserved0 [31:01] */
#define DDR23_PHY_ADDR_CTL_PLL_STATUS_RESERVED0_MASK               0xfffffffe
#define DDR23_PHY_ADDR_CTL_PLL_STATUS_RESERVED0_ALIGN              0
#define DDR23_PHY_ADDR_CTL_PLL_STATUS_RESERVED0_BITS               31
#define DDR23_PHY_ADDR_CTL_PLL_STATUS_RESERVED0_SHIFT              1

/* DDR23_PHY_ADDR_CTL :: PLL_STATUS :: LOCK [00:00] */
#define DDR23_PHY_ADDR_CTL_PLL_STATUS_LOCK_MASK                    0x00000001
#define DDR23_PHY_ADDR_CTL_PLL_STATUS_LOCK_ALIGN                   0
#define DDR23_PHY_ADDR_CTL_PLL_STATUS_LOCK_BITS                    1
#define DDR23_PHY_ADDR_CTL_PLL_STATUS_LOCK_SHIFT                   0


/****************************************************************************
 * DDR23_PHY_ADDR_CTL :: PLL_CONFIG
 ***************************************************************************/
/* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: DIV2_CLK_RESET [31:31] */
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_DIV2_CLK_RESET_MASK          0x80000000
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_DIV2_CLK_RESET_ALIGN         0
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_DIV2_CLK_RESET_BITS          1
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_DIV2_CLK_RESET_SHIFT         31

/* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: reserved0 [30:22] */
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED0_MASK               0x7fc00000
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED0_ALIGN              0
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED0_BITS               9
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED0_SHIFT              22

/* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: TEST_SEL [21:17] */
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_TEST_SEL_MASK                0x003e0000
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_TEST_SEL_ALIGN               0
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_TEST_SEL_BITS                5
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_TEST_SEL_SHIFT               17

/* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: TEST_EN [16:16] */
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_TEST_EN_MASK                 0x00010000
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_TEST_EN_ALIGN                0
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_TEST_EN_BITS                 1
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_TEST_EN_SHIFT                16

/* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: BGAP_ADJ [15:12] */
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_BGAP_ADJ_MASK                0x0000f000
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_BGAP_ADJ_ALIGN               0
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_BGAP_ADJ_BITS                4
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_BGAP_ADJ_SHIFT               12

/* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: reserved1 [11:08] */
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED1_MASK               0x00000f00
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED1_ALIGN              0
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED1_BITS               4
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED1_SHIFT              8

/* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: VCO_RNG [07:07] */
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_VCO_RNG_MASK                 0x00000080
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_VCO_RNG_ALIGN                0
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_VCO_RNG_BITS                 1
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_VCO_RNG_SHIFT                7

/* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: PWRDN_CH1 [06:06] */
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_PWRDN_CH1_MASK               0x00000040
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_PWRDN_CH1_ALIGN              0
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_PWRDN_CH1_BITS               1
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_PWRDN_CH1_SHIFT              6

/* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: BYPEN [05:05] */
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_BYPEN_MASK                   0x00000020
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_BYPEN_ALIGN                  0
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_BYPEN_BITS                   1
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_BYPEN_SHIFT                  5

/* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: ENB_CLKOUT [04:04] */
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_ENB_CLKOUT_MASK              0x00000010
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_ENB_CLKOUT_ALIGN             0
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_ENB_CLKOUT_BITS              1
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_ENB_CLKOUT_SHIFT             4

/* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: DRESET [03:03] */
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_DRESET_MASK                  0x00000008
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_DRESET_ALIGN                 0
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_DRESET_BITS                  1
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_DRESET_SHIFT                 3

/* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: ARESET [02:02] */
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_ARESET_MASK                  0x00000004
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_ARESET_ALIGN                 0
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_ARESET_BITS                  1
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_ARESET_SHIFT                 2

/* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: reserved2 [01:01] */
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED2_MASK               0x00000002
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED2_ALIGN              0
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED2_BITS               1
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED2_SHIFT              1

/* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: PWRDN [00:00] */
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_PWRDN_MASK                   0x00000001
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_PWRDN_ALIGN                  0
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_PWRDN_BITS                   1
#define DDR23_PHY_ADDR_CTL_PLL_CONFIG_PWRDN_SHIFT                  0


/****************************************************************************
 * DDR23_PHY_ADDR_CTL :: PLL_PRE_DIVIDER
 ***************************************************************************/
/* DDR23_PHY_ADDR_CTL :: PLL_PRE_DIVIDER :: reserved0 [31:27] */
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED0_MASK          0xf8000000
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED0_ALIGN         0
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED0_BITS          5
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED0_SHIFT         27

/* DDR23_PHY_ADDR_CTL :: PLL_PRE_DIVIDER :: NDIV_DITHER_MFB [26:26] */
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_DITHER_MFB_MASK    0x04000000
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_DITHER_MFB_ALIGN   0
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_DITHER_MFB_BITS    1
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_DITHER_MFB_SHIFT   26

/* DDR23_PHY_ADDR_CTL :: PLL_PRE_DIVIDER :: NDIV_PWRDN [25:25] */
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_PWRDN_MASK         0x02000000
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_PWRDN_ALIGN        0
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_PWRDN_BITS         1
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_PWRDN_SHIFT        25

/* DDR23_PHY_ADDR_CTL :: PLL_PRE_DIVIDER :: reserved1 [24:23] */
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED1_MASK          0x01800000
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED1_ALIGN         0
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED1_BITS          2
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED1_SHIFT         23

/* DDR23_PHY_ADDR_CTL :: PLL_PRE_DIVIDER :: NDIV_MODE [22:20] */
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_MODE_MASK          0x00700000
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_MODE_ALIGN         0
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_MODE_BITS          3
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_MODE_SHIFT         20

/* DDR23_PHY_ADDR_CTL :: PLL_PRE_DIVIDER :: reserved2 [19:17] */
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED2_MASK          0x000e0000
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED2_ALIGN         0
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED2_BITS          3
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED2_SHIFT         17

/* DDR23_PHY_ADDR_CTL :: PLL_PRE_DIVIDER :: NDIV_INT [16:08] */
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_INT_MASK           0x0001ff00
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_INT_ALIGN          0
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_INT_BITS           9
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_INT_SHIFT          8

/* DDR23_PHY_ADDR_CTL :: PLL_PRE_DIVIDER :: P2DIV [07:04] */
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_P2DIV_MASK              0x000000f0
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_P2DIV_ALIGN             0
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_P2DIV_BITS              4
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_P2DIV_SHIFT             4

/* DDR23_PHY_ADDR_CTL :: PLL_PRE_DIVIDER :: P1DIV [03:00] */
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_P1DIV_MASK              0x0000000f
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_P1DIV_ALIGN             0
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_P1DIV_BITS              4
#define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_P1DIV_SHIFT             0


/****************************************************************************
 * DDR23_PHY_ADDR_CTL :: PLL_DIVIDER
 ***************************************************************************/
/* DDR23_PHY_ADDR_CTL :: PLL_DIVIDER :: M1DIV [31:24] */
#define DDR23_PHY_ADDR_CTL_PLL_DIVIDER_M1DIV_MASK                  0xff000000
#define DDR23_PHY_ADDR_CTL_PLL_DIVIDER_M1DIV_ALIGN                 0
#define DDR23_PHY_ADDR_CTL_PLL_DIVIDER_M1DIV_BITS                  8
#define DDR23_PHY_ADDR_CTL_PLL_DIVIDER_M1DIV_SHIFT                 24

/* DDR23_PHY_ADDR_CTL :: PLL_DIVIDER :: NDIV_FRAC [23:00] */
#define DDR23_PHY_ADDR_CTL_PLL_DIVIDER_NDIV_FRAC_MASK              0x00ffffff
#define DDR23_PHY_ADDR_CTL_PLL_DIVIDER_NDIV_FRAC_ALIGN             0
#define DDR23_PHY_ADDR_CTL_PLL_DIVIDER_NDIV_FRAC_BITS              24
#define DDR23_PHY_ADDR_CTL_PLL_DIVIDER_NDIV_FRAC_SHIFT             0


/****************************************************************************
 * DDR23_PHY_ADDR_CTL :: PLL_CONTROL1
 ***************************************************************************/
/* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: TESTA_SEL [31:30] */
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_TESTA_SEL_MASK             0xc0000000
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_TESTA_SEL_ALIGN            0
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_TESTA_SEL_BITS             2
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_TESTA_SEL_SHIFT            30

/* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: KVCO_XS [29:27] */
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_KVCO_XS_MASK               0x38000000
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_KVCO_XS_ALIGN              0
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_KVCO_XS_BITS               3
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_KVCO_XS_SHIFT              27

/* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: KVCO_XF [26:24] */
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_KVCO_XF_MASK               0x07000000
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_KVCO_XF_ALIGN              0
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_KVCO_XF_BITS               3
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_KVCO_XF_SHIFT              24

/* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: LPF_BW [23:22] */
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_LPF_BW_MASK                0x00c00000
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_LPF_BW_ALIGN               0
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_LPF_BW_BITS                2
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_LPF_BW_SHIFT               22

/* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: LF_ORDER [21:21] */
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_LF_ORDER_MASK              0x00200000
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_LF_ORDER_ALIGN             0
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_LF_ORDER_BITS              1
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_LF_ORDER_SHIFT             21

/* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: CN [20:19] */
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CN_MASK                    0x00180000
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CN_ALIGN                   0
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CN_BITS                    2
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CN_SHIFT                   19

/* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: RN [18:17] */
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_RN_MASK                    0x00060000
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_RN_ALIGN                   0
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_RN_BITS                    2
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_RN_SHIFT                   17

/* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: CP [16:15] */
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CP_MASK                    0x00018000
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CP_ALIGN                   0
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CP_BITS                    2
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CP_SHIFT                   15

/* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: CZ [14:13] */
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CZ_MASK                    0x00006000
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CZ_ALIGN                   0
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CZ_BITS                    2
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CZ_SHIFT                   13

/* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: RZ [12:10] */
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_RZ_MASK                    0x00001c00
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_RZ_ALIGN                   0
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_RZ_BITS                    3
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_RZ_SHIFT                   10

/* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: ICPX [09:05] */
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_ICPX_MASK                  0x000003e0
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_ICPX_ALIGN                 0
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_ICPX_BITS                  5
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_ICPX_SHIFT                 5

/* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: ICP_OFF [04:00] */
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_ICP_OFF_MASK               0x0000001f
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_ICP_OFF_ALIGN              0
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_ICP_OFF_BITS               5
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_ICP_OFF_SHIFT              0


/****************************************************************************
 * DDR23_PHY_ADDR_CTL :: PLL_CONTROL2
 ***************************************************************************/
/* DDR23_PHY_ADDR_CTL :: PLL_CONTROL2 :: reserved0 [31:06] */
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_RESERVED0_MASK             0xffffffc0
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_RESERVED0_ALIGN            0
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_RESERVED0_BITS             26
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_RESERVED0_SHIFT            6

/* DDR23_PHY_ADDR_CTL :: PLL_CONTROL2 :: PTAP_ADJ [05:04] */
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_PTAP_ADJ_MASK              0x00000030
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_PTAP_ADJ_ALIGN             0
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_PTAP_ADJ_BITS              2
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_PTAP_ADJ_SHIFT             4

/* DDR23_PHY_ADDR_CTL :: PLL_CONTROL2 :: CTAP_ADJ [03:02] */
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_CTAP_ADJ_MASK              0x0000000c
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_CTAP_ADJ_ALIGN             0
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_CTAP_ADJ_BITS              2
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_CTAP_ADJ_SHIFT             2

/* DDR23_PHY_ADDR_CTL :: PLL_CONTROL2 :: LOWCUR_EN [01:01] */
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_LOWCUR_EN_MASK             0x00000002
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_LOWCUR_EN_ALIGN            0
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_LOWCUR_EN_BITS             1
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_LOWCUR_EN_SHIFT            1

/* DDR23_PHY_ADDR_CTL :: PLL_CONTROL2 :: BIASIN_EN [00:00] */
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_BIASIN_EN_MASK             0x00000001
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_BIASIN_EN_ALIGN            0
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_BIASIN_EN_BITS             1
#define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_BIASIN_EN_SHIFT            0


/****************************************************************************
 * DDR23_PHY_ADDR_CTL :: PLL_SS_EN
 ***************************************************************************/
/* DDR23_PHY_ADDR_CTL :: PLL_SS_EN :: reserved0 [31:01] */
#define DDR23_PHY_ADDR_CTL_PLL_SS_EN_RESERVED0_MASK                0xfffffffe
#define DDR23_PHY_ADDR_CTL_PLL_SS_EN_RESERVED0_ALIGN               0
#define DDR23_PHY_ADDR_CTL_PLL_SS_EN_RESERVED0_BITS                31
#define DDR23_PHY_ADDR_CTL_PLL_SS_EN_RESERVED0_SHIFT               1

/* DDR23_PHY_ADDR_CTL :: PLL_SS_EN :: SS_EN [00:00] */
#define DDR23_PHY_ADDR_CTL_PLL_SS_EN_SS_EN_MASK                    0x00000001
#define DDR23_PHY_ADDR_CTL_PLL_SS_EN_SS_EN_ALIGN                   0
#define DDR23_PHY_ADDR_CTL_PLL_SS_EN_SS_EN_BITS                    1
#define DDR23_PHY_ADDR_CTL_PLL_SS_EN_SS_EN_SHIFT                   0


/****************************************************************************
 * DDR23_PHY_ADDR_CTL :: PLL_SS_CFG
 ***************************************************************************/
/* DDR23_PHY_ADDR_CTL :: PLL_SS_CFG :: REF_CYC_PER_TICK [31:16] */
#define DDR23_PHY_ADDR_CTL_PLL_SS_CFG_REF_CYC_PER_TICK_MASK        0xffff0000
#define DDR23_PHY_ADDR_CTL_PLL_SS_CFG_REF_CYC_PER_TICK_ALIGN       0
#define DDR23_PHY_ADDR_CTL_PLL_SS_CFG_REF_CYC_PER_TICK_BITS        16
#define DDR23_PHY_ADDR_CTL_PLL_SS_CFG_REF_CYC_PER_TICK_SHIFT       16

/* DDR23_PHY_ADDR_CTL :: PLL_SS_CFG :: NDIV_AMP [15:00] */
#define DDR23_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_MASK                0x0000ffff
#define DDR23_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_ALIGN               0
#define DDR23_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_BITS                16
#define DDR23_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT               0


/****************************************************************************
 * DDR23_PHY_ADDR_CTL :: STATIC_VDL_OVERRIDE
 ***************************************************************************/
/* DDR23_PHY_ADDR_CTL :: STATIC_VDL_OVERRIDE :: reserved0 [31:21] */
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED0_MASK      0xffe00000
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED0_ALIGN     0
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED0_BITS      11
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED0_SHIFT     21

/* DDR23_PHY_ADDR_CTL :: STATIC_VDL_OVERRIDE :: ovr_force [20:20] */
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FORCE_MASK      0x00100000
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FORCE_ALIGN     0
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FORCE_BITS      1
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FORCE_SHIFT     20

/* DDR23_PHY_ADDR_CTL :: STATIC_VDL_OVERRIDE :: reserved1 [19:17] */
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED1_MASK      0x000e0000
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED1_ALIGN     0
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED1_BITS      3
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED1_SHIFT     17

/* DDR23_PHY_ADDR_CTL :: STATIC_VDL_OVERRIDE :: ovr_en [16:16] */
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_EN_MASK         0x00010000
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_EN_ALIGN        0
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_EN_BITS         1
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_EN_SHIFT        16

/* DDR23_PHY_ADDR_CTL :: STATIC_VDL_OVERRIDE :: reserved2 [15:14] */
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED2_MASK      0x0000c000
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED2_ALIGN     0
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED2_BITS      2
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED2_SHIFT     14

/* DDR23_PHY_ADDR_CTL :: STATIC_VDL_OVERRIDE :: ovr_fine_fall [13:12] */
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FINE_FALL_MASK  0x00003000
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FINE_FALL_ALIGN 0
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FINE_FALL_BITS  2
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FINE_FALL_SHIFT 12

/* DDR23_PHY_ADDR_CTL :: STATIC_VDL_OVERRIDE :: reserved3 [11:10] */
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED3_MASK      0x00000c00
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED3_ALIGN     0
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED3_BITS      2
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED3_SHIFT     10

/* DDR23_PHY_ADDR_CTL :: STATIC_VDL_OVERRIDE :: ovr_fine_rise [09:08] */
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FINE_RISE_MASK  0x00000300
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FINE_RISE_ALIGN 0
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FINE_RISE_BITS  2
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FINE_RISE_SHIFT 8

/* DDR23_PHY_ADDR_CTL :: STATIC_VDL_OVERRIDE :: reserved4 [07:06] */
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED4_MASK      0x000000c0
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED4_ALIGN     0
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED4_BITS      2
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED4_SHIFT     6

/* DDR23_PHY_ADDR_CTL :: STATIC_VDL_OVERRIDE :: ovr_step [05:00] */
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_STEP_MASK       0x0000003f
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_STEP_ALIGN      0
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_STEP_BITS       6
#define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_STEP_SHIFT      0


/****************************************************************************
 * DDR23_PHY_ADDR_CTL :: DYNAMIC_VDL_OVERRIDE
 ***************************************************************************/
/* DDR23_PHY_ADDR_CTL :: DYNAMIC_VDL_OVERRIDE :: reserved0 [31:17] */
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED0_MASK     0xfffe0000
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED0_ALIGN    0
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED0_BITS     15
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED0_SHIFT    17

/* DDR23_PHY_ADDR_CTL :: DYNAMIC_VDL_OVERRIDE :: ovr_en [16:16] */
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_EN_MASK        0x00010000
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_EN_ALIGN       0
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_EN_BITS        1
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_EN_SHIFT       16

/* DDR23_PHY_ADDR_CTL :: DYNAMIC_VDL_OVERRIDE :: reserved1 [15:14] */
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED1_MASK     0x0000c000
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED1_ALIGN    0
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED1_BITS     2
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED1_SHIFT    14

/* DDR23_PHY_ADDR_CTL :: DYNAMIC_VDL_OVERRIDE :: ovr_fine_fall [13:12] */
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_FINE_FALL_MASK 0x00003000
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_FINE_FALL_ALIGN 0
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_FINE_FALL_BITS 2
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_FINE_FALL_SHIFT 12

/* DDR23_PHY_ADDR_CTL :: DYNAMIC_VDL_OVERRIDE :: reserved2 [11:10] */
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED2_MASK     0x00000c00
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED2_ALIGN    0
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED2_BITS     2
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED2_SHIFT    10

/* DDR23_PHY_ADDR_CTL :: DYNAMIC_VDL_OVERRIDE :: ovr_fine_rise [09:08] */
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_FINE_RISE_MASK 0x00000300
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_FINE_RISE_ALIGN 0
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_FINE_RISE_BITS 2
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_FINE_RISE_SHIFT 8

/* DDR23_PHY_ADDR_CTL :: DYNAMIC_VDL_OVERRIDE :: reserved3 [07:06] */
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED3_MASK     0x000000c0
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED3_ALIGN    0
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED3_BITS     2
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED3_SHIFT    6

/* DDR23_PHY_ADDR_CTL :: DYNAMIC_VDL_OVERRIDE :: ovr_step [05:00] */
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_STEP_MASK      0x0000003f
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_STEP_ALIGN     0
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_STEP_BITS      6
#define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_STEP_SHIFT     0


/****************************************************************************
 * DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL
 ***************************************************************************/
/* DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL :: idle [31:31] */
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_IDLE_MASK              0x80000000
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_IDLE_ALIGN             0
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_IDLE_BITS              1
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_IDLE_SHIFT             31

/* DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL :: reserved0 [30:09] */
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED0_MASK         0x7ffffe00
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED0_ALIGN        0
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED0_BITS         22
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED0_SHIFT        9

/* DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL :: rxenb [08:08] */
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RXENB_MASK             0x00000100
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RXENB_ALIGN            0
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RXENB_BITS             1
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RXENB_SHIFT            8

/* DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL :: reserved1 [07:07] */
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED1_MASK         0x00000080
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED1_ALIGN        0
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED1_BITS         1
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED1_SHIFT        7

/* DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_IDDQ_MASK          0x00000040
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_IDDQ_ALIGN         0
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_IDDQ_BITS          1
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_IDDQ_SHIFT         6

/* DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_REB_MASK           0x00000020
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_REB_ALIGN          0
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_REB_BITS           1
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_REB_SHIFT          5

/* DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_OEB_MASK           0x00000010
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_OEB_ALIGN          0
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_OEB_BITS           1
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_OEB_SHIFT          4

/* DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL :: reserved2 [03:03] */
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED2_MASK         0x00000008
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED2_ALIGN        0
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED2_BITS         1
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED2_SHIFT        3

/* DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_IDDQ_MASK          0x00000004
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_IDDQ_ALIGN         0
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_IDDQ_BITS          1
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_IDDQ_SHIFT         2

/* DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL :: cke_reb [01:01] */
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_REB_MASK           0x00000002
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_REB_ALIGN          0
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_REB_BITS           1
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_REB_SHIFT          1

/* DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_OEB_MASK           0x00000001
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_OEB_ALIGN          0
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_OEB_BITS           1
#define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_OEB_SHIFT          0


/****************************************************************************
 * DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL
 ***************************************************************************/
/* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: reserved0 [31:31] */
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_RESERVED0_MASK          0x80000000
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_RESERVED0_ALIGN         0
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_RESERVED0_BITS          1
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_RESERVED0_SHIFT         31

/* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: pd_done [30:30] */
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_PD_DONE_MASK            0x40000000
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_PD_DONE_ALIGN           0
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_PD_DONE_BITS            1
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_PD_DONE_SHIFT           30

/* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: nd_done [29:29] */
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ND_DONE_MASK            0x20000000
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ND_DONE_ALIGN           0
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ND_DONE_BITS            1
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ND_DONE_SHIFT           29

/* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: sample_done [28:28] */
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_SAMPLE_DONE_MASK        0x10000000
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_SAMPLE_DONE_ALIGN       0
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_SAMPLE_DONE_BITS        1
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_SAMPLE_DONE_SHIFT       28

/* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: auto_sample_en [27:27] */
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_AUTO_SAMPLE_EN_MASK     0x08000000
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_AUTO_SAMPLE_EN_ALIGN    0
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_AUTO_SAMPLE_EN_BITS     1
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_AUTO_SAMPLE_EN_SHIFT    27

/* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: sample_en [26:26] */
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_SAMPLE_EN_MASK          0x04000000
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_SAMPLE_EN_ALIGN         0
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_SAMPLE_EN_BITS          1
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_SAMPLE_EN_SHIFT         26

/* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: addr_ovr_en [25:25] */
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_OVR_EN_MASK        0x02000000
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_OVR_EN_ALIGN       0
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_OVR_EN_BITS        1
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_OVR_EN_SHIFT       25

/* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: dq_ovr_en [24:24] */
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_OVR_EN_MASK          0x01000000
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_OVR_EN_ALIGN         0
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_OVR_EN_BITS          1
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_OVR_EN_SHIFT         24

/* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: pd_comp [23:20] */
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_PD_COMP_MASK            0x00f00000
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_PD_COMP_ALIGN           0
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_PD_COMP_BITS            4
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_PD_COMP_SHIFT           20

/* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: nd_comp [19:16] */
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ND_COMP_MASK            0x000f0000
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ND_COMP_ALIGN           0
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ND_COMP_BITS            4
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ND_COMP_SHIFT           16

/* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [15:12] */
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_PD_OVERRIDE_VAL_MASK 0x0000f000
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_PD_OVERRIDE_VAL_ALIGN 0
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_PD_OVERRIDE_VAL_BITS 4
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_PD_OVERRIDE_VAL_SHIFT 12

/* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [11:08] */
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_ND_OVERRIDE_VAL_MASK 0x00000f00
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_ND_OVERRIDE_VAL_ALIGN 0
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_ND_OVERRIDE_VAL_BITS 4
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_ND_OVERRIDE_VAL_SHIFT 8

/* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [07:04] */
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_PD_OVERRIDE_VAL_MASK 0x000000f0
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_PD_OVERRIDE_VAL_ALIGN 0
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_PD_OVERRIDE_VAL_BITS 4
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_PD_OVERRIDE_VAL_SHIFT 4

/* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [03:00] */
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_ND_OVERRIDE_VAL_MASK 0x0000000f
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_ND_OVERRIDE_VAL_ALIGN 0
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_ND_OVERRIDE_VAL_BITS 4
#define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_ND_OVERRIDE_VAL_SHIFT 0


/****************************************************************************
 * DDR23_PHY_ADDR_CTL :: DRIVE_PAD_CTL
 ***************************************************************************/
/* DDR23_PHY_ADDR_CTL :: DRIVE_PAD_CTL :: reserved0 [31:05] */
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_RESERVED0_MASK            0xffffffe0
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_RESERVED0_ALIGN           0
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_RESERVED0_BITS            27
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_RESERVED0_SHIFT           5

/* DDR23_PHY_ADDR_CTL :: DRIVE_PAD_CTL :: rt60b [04:04] */
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_RT60B_MASK                0x00000010
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_RT60B_ALIGN               0
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_RT60B_BITS                1
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_RT60B_SHIFT               4

/* DDR23_PHY_ADDR_CTL :: DRIVE_PAD_CTL :: sel_sstl18 [03:03] */
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SEL_SSTL18_MASK           0x00000008
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SEL_SSTL18_ALIGN          0
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SEL_SSTL18_BITS           1
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SEL_SSTL18_SHIFT          3

/* DDR23_PHY_ADDR_CTL :: DRIVE_PAD_CTL :: seltxdrv_ci [02:02] */
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SELTXDRV_CI_MASK          0x00000004
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SELTXDRV_CI_ALIGN         0
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SELTXDRV_CI_BITS          1
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SELTXDRV_CI_SHIFT         2

/* DDR23_PHY_ADDR_CTL :: DRIVE_PAD_CTL :: selrxdrv [01:01] */
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SELRXDRV_MASK             0x00000002
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SELRXDRV_ALIGN            0
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SELRXDRV_BITS             1
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SELRXDRV_SHIFT            1

/* DDR23_PHY_ADDR_CTL :: DRIVE_PAD_CTL :: slew [00:00] */
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SLEW_MASK                 0x00000001
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SLEW_ALIGN                0
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SLEW_BITS                 1
#define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SLEW_SHIFT                0


/****************************************************************************
 * DDR23_PHY_ADDR_CTL :: CLOCK_REG_CONTROL
 ***************************************************************************/
/* DDR23_PHY_ADDR_CTL :: CLOCK_REG_CONTROL :: reserved0 [31:02] */
#define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_RESERVED0_MASK        0xfffffffc
#define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_RESERVED0_ALIGN       0
#define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_RESERVED0_BITS        30
#define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_RESERVED0_SHIFT       2

/* DDR23_PHY_ADDR_CTL :: CLOCK_REG_CONTROL :: half_power [01:01] */
#define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_HALF_POWER_MASK       0x00000002
#define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_HALF_POWER_ALIGN      0
#define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_HALF_POWER_BITS       1
#define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_HALF_POWER_SHIFT      1

/* DDR23_PHY_ADDR_CTL :: CLOCK_REG_CONTROL :: pwrdn [00:00] */
#define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_PWRDN_MASK            0x00000001
#define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_PWRDN_ALIGN           0
#define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_PWRDN_BITS            1
#define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_PWRDN_SHIFT           0


/****************************************************************************
 * DDR23_PHY_DDR23_PHY_BYTE_LANE0
 ***************************************************************************/
/****************************************************************************
 * DDR23_PHY_BYTE_LANE0 :: REVISION
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE0 :: REVISION :: reserved0 [31:16] */
#define DDR23_PHY_BYTE_LANE0_REVISION_RESERVED0_MASK               0xffff0000
#define DDR23_PHY_BYTE_LANE0_REVISION_RESERVED0_ALIGN              0
#define DDR23_PHY_BYTE_LANE0_REVISION_RESERVED0_BITS               16
#define DDR23_PHY_BYTE_LANE0_REVISION_RESERVED0_SHIFT              16

/* DDR23_PHY_BYTE_LANE0 :: REVISION :: MAJOR [15:08] */
#define DDR23_PHY_BYTE_LANE0_REVISION_MAJOR_MASK                   0x0000ff00
#define DDR23_PHY_BYTE_LANE0_REVISION_MAJOR_ALIGN                  0
#define DDR23_PHY_BYTE_LANE0_REVISION_MAJOR_BITS                   8
#define DDR23_PHY_BYTE_LANE0_REVISION_MAJOR_SHIFT                  8

/* DDR23_PHY_BYTE_LANE0 :: REVISION :: MINOR [07:00] */
#define DDR23_PHY_BYTE_LANE0_REVISION_MINOR_MASK                   0x000000ff
#define DDR23_PHY_BYTE_LANE0_REVISION_MINOR_ALIGN                  0
#define DDR23_PHY_BYTE_LANE0_REVISION_MINOR_BITS                   8
#define DDR23_PHY_BYTE_LANE0_REVISION_MINOR_SHIFT                  0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE0 :: VDL_CALIBRATE
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE0 :: VDL_CALIBRATE :: reserved0 [31:05] */
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_RESERVED0_MASK          0xffffffe0
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_RESERVED0_ALIGN         0
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_RESERVED0_BITS          27
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_RESERVED0_SHIFT         5

/* DDR23_PHY_BYTE_LANE0 :: VDL_CALIBRATE :: calib_clocks [04:04] */
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_CLOCKS_MASK       0x00000010
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_CLOCKS_ALIGN      0
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_CLOCKS_BITS       1
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_CLOCKS_SHIFT      4

/* DDR23_PHY_BYTE_LANE0 :: VDL_CALIBRATE :: calib_test [03:03] */
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_TEST_MASK         0x00000008
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_TEST_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_TEST_BITS         1
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_TEST_SHIFT        3

/* DDR23_PHY_BYTE_LANE0 :: VDL_CALIBRATE :: calib_always [02:02] */
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_ALWAYS_MASK       0x00000004
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_ALWAYS_ALIGN      0
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_ALWAYS_BITS       1
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_ALWAYS_SHIFT      2

/* DDR23_PHY_BYTE_LANE0 :: VDL_CALIBRATE :: calib_once [01:01] */
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_ONCE_MASK         0x00000002
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_ONCE_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_ONCE_BITS         1
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_ONCE_SHIFT        1

/* DDR23_PHY_BYTE_LANE0 :: VDL_CALIBRATE :: calib_fast [00:00] */
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_FAST_MASK         0x00000001
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_FAST_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_FAST_BITS         1
#define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_FAST_SHIFT        0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE0 :: VDL_STATUS
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE0 :: VDL_STATUS :: reserved0 [31:14] */
#define DDR23_PHY_BYTE_LANE0_VDL_STATUS_RESERVED0_MASK             0xffffc000
#define DDR23_PHY_BYTE_LANE0_VDL_STATUS_RESERVED0_ALIGN            0
#define DDR23_PHY_BYTE_LANE0_VDL_STATUS_RESERVED0_BITS             18
#define DDR23_PHY_BYTE_LANE0_VDL_STATUS_RESERVED0_SHIFT            14

/* DDR23_PHY_BYTE_LANE0 :: VDL_STATUS :: calib_total [13:04] */
#define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_TOTAL_MASK           0x00003ff0
#define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_TOTAL_ALIGN          0
#define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_TOTAL_BITS           10
#define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_TOTAL_SHIFT          4

/* DDR23_PHY_BYTE_LANE0 :: VDL_STATUS :: reserved1 [03:02] */
#define DDR23_PHY_BYTE_LANE0_VDL_STATUS_RESERVED1_MASK             0x0000000c
#define DDR23_PHY_BYTE_LANE0_VDL_STATUS_RESERVED1_ALIGN            0
#define DDR23_PHY_BYTE_LANE0_VDL_STATUS_RESERVED1_BITS             2
#define DDR23_PHY_BYTE_LANE0_VDL_STATUS_RESERVED1_SHIFT            2

/* DDR23_PHY_BYTE_LANE0 :: VDL_STATUS :: calib_lock [01:01] */
#define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_LOCK_MASK            0x00000002
#define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_LOCK_ALIGN           0
#define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_LOCK_BITS            1
#define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_LOCK_SHIFT           1

/* DDR23_PHY_BYTE_LANE0 :: VDL_STATUS :: calib_idle [00:00] */
#define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_IDLE_MASK            0x00000001
#define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_IDLE_ALIGN           0
#define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_IDLE_BITS            1
#define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_IDLE_SHIFT           0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_0
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_0 :: reserved0 [31:17] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED0_MASK         0xfffe0000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED0_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED0_BITS         15
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED0_SHIFT        17

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_0 :: ovr_en [16:16] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_EN_MASK            0x00010000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_EN_ALIGN           0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_EN_BITS            1
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_EN_SHIFT           16

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_0 :: reserved1 [15:14] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED1_MASK         0x0000c000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED1_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED1_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED1_SHIFT        14

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_0 :: ovr_fine_fall [13:12] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_FINE_FALL_MASK     0x00003000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_FINE_FALL_ALIGN    0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_FINE_FALL_BITS     2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_FINE_FALL_SHIFT    12

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_0 :: reserved2 [11:10] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED2_MASK         0x00000c00
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED2_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED2_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED2_SHIFT        10

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_0 :: ovr_fine_rise [09:08] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_FINE_RISE_MASK     0x00000300
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_FINE_RISE_ALIGN    0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_FINE_RISE_BITS     2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_FINE_RISE_SHIFT    8

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_0 :: reserved3 [07:06] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED3_MASK         0x000000c0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED3_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED3_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED3_SHIFT        6

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_0 :: ovr_step [05:00] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_STEP_MASK          0x0000003f
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_STEP_ALIGN         0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_STEP_BITS          6
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_STEP_SHIFT         0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_1
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_1 :: reserved0 [31:17] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED0_MASK         0xfffe0000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED0_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED0_BITS         15
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED0_SHIFT        17

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_1 :: ovr_en [16:16] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_EN_MASK            0x00010000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_EN_ALIGN           0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_EN_BITS            1
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_EN_SHIFT           16

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_1 :: reserved1 [15:14] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED1_MASK         0x0000c000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED1_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED1_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED1_SHIFT        14

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_1 :: ovr_fine_fall [13:12] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_FINE_FALL_MASK     0x00003000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_FINE_FALL_ALIGN    0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_FINE_FALL_BITS     2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_FINE_FALL_SHIFT    12

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_1 :: reserved2 [11:10] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED2_MASK         0x00000c00
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED2_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED2_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED2_SHIFT        10

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_1 :: ovr_fine_rise [09:08] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_FINE_RISE_MASK     0x00000300
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_FINE_RISE_ALIGN    0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_FINE_RISE_BITS     2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_FINE_RISE_SHIFT    8

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_1 :: reserved3 [07:06] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED3_MASK         0x000000c0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED3_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED3_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED3_SHIFT        6

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_1 :: ovr_step [05:00] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_STEP_MASK          0x0000003f
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_STEP_ALIGN         0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_STEP_BITS          6
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_STEP_SHIFT         0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_2
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_2 :: reserved0 [31:17] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED0_MASK         0xfffe0000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED0_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED0_BITS         15
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED0_SHIFT        17

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_2 :: ovr_en [16:16] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_EN_MASK            0x00010000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_EN_ALIGN           0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_EN_BITS            1
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_EN_SHIFT           16

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_2 :: reserved1 [15:14] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED1_MASK         0x0000c000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED1_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED1_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED1_SHIFT        14

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_2 :: ovr_fine_fall [13:12] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_FINE_FALL_MASK     0x00003000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_FINE_FALL_ALIGN    0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_FINE_FALL_BITS     2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_FINE_FALL_SHIFT    12

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_2 :: reserved2 [11:10] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED2_MASK         0x00000c00
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED2_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED2_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED2_SHIFT        10

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_2 :: ovr_fine_rise [09:08] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_FINE_RISE_MASK     0x00000300
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_FINE_RISE_ALIGN    0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_FINE_RISE_BITS     2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_FINE_RISE_SHIFT    8

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_2 :: reserved3 [07:06] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED3_MASK         0x000000c0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED3_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED3_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED3_SHIFT        6

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_2 :: ovr_step [05:00] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_STEP_MASK          0x0000003f
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_STEP_ALIGN         0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_STEP_BITS          6
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_STEP_SHIFT         0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_3
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_3 :: reserved0 [31:17] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED0_MASK         0xfffe0000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED0_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED0_BITS         15
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED0_SHIFT        17

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_3 :: ovr_en [16:16] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_EN_MASK            0x00010000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_EN_ALIGN           0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_EN_BITS            1
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_EN_SHIFT           16

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_3 :: reserved1 [15:14] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED1_MASK         0x0000c000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED1_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED1_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED1_SHIFT        14

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_3 :: ovr_fine_fall [13:12] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_FINE_FALL_MASK     0x00003000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_FINE_FALL_ALIGN    0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_FINE_FALL_BITS     2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_FINE_FALL_SHIFT    12

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_3 :: reserved2 [11:10] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED2_MASK         0x00000c00
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED2_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED2_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED2_SHIFT        10

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_3 :: ovr_fine_rise [09:08] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_FINE_RISE_MASK     0x00000300
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_FINE_RISE_ALIGN    0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_FINE_RISE_BITS     2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_FINE_RISE_SHIFT    8

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_3 :: reserved3 [07:06] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED3_MASK         0x000000c0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED3_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED3_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED3_SHIFT        6

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_3 :: ovr_step [05:00] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_STEP_MASK          0x0000003f
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_STEP_ALIGN         0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_STEP_BITS          6
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_STEP_SHIFT         0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_4
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_4 :: reserved0 [31:17] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED0_MASK         0xfffe0000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED0_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED0_BITS         15
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED0_SHIFT        17

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_4 :: ovr_en [16:16] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_EN_MASK            0x00010000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_EN_ALIGN           0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_EN_BITS            1
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_EN_SHIFT           16

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_4 :: reserved1 [15:14] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED1_MASK         0x0000c000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED1_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED1_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED1_SHIFT        14

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_4 :: ovr_fine_fall [13:12] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_FINE_FALL_MASK     0x00003000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_FINE_FALL_ALIGN    0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_FINE_FALL_BITS     2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_FINE_FALL_SHIFT    12

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_4 :: reserved2 [11:10] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED2_MASK         0x00000c00
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED2_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED2_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED2_SHIFT        10

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_4 :: ovr_fine_rise [09:08] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_FINE_RISE_MASK     0x00000300
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_FINE_RISE_ALIGN    0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_FINE_RISE_BITS     2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_FINE_RISE_SHIFT    8

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_4 :: reserved3 [07:06] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED3_MASK         0x000000c0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED3_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED3_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED3_SHIFT        6

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_4 :: ovr_step [05:00] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_STEP_MASK          0x0000003f
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_STEP_ALIGN         0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_STEP_BITS          6
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_STEP_SHIFT         0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_5
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_5 :: reserved0 [31:17] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED0_MASK         0xfffe0000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED0_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED0_BITS         15
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED0_SHIFT        17

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_5 :: ovr_en [16:16] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_EN_MASK            0x00010000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_EN_ALIGN           0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_EN_BITS            1
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_EN_SHIFT           16

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_5 :: reserved1 [15:14] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED1_MASK         0x0000c000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED1_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED1_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED1_SHIFT        14

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_5 :: ovr_fine_fall [13:12] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_FINE_FALL_MASK     0x00003000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_FINE_FALL_ALIGN    0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_FINE_FALL_BITS     2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_FINE_FALL_SHIFT    12

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_5 :: reserved2 [11:10] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED2_MASK         0x00000c00
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED2_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED2_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED2_SHIFT        10

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_5 :: ovr_fine_rise [09:08] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_FINE_RISE_MASK     0x00000300
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_FINE_RISE_ALIGN    0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_FINE_RISE_BITS     2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_FINE_RISE_SHIFT    8

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_5 :: reserved3 [07:06] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED3_MASK         0x000000c0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED3_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED3_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED3_SHIFT        6

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_5 :: ovr_step [05:00] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_STEP_MASK          0x0000003f
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_STEP_ALIGN         0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_STEP_BITS          6
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_STEP_SHIFT         0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_6
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_6 :: reserved0 [31:17] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED0_MASK         0xfffe0000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED0_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED0_BITS         15
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED0_SHIFT        17

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_6 :: ovr_en [16:16] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_EN_MASK            0x00010000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_EN_ALIGN           0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_EN_BITS            1
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_EN_SHIFT           16

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_6 :: reserved1 [15:14] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED1_MASK         0x0000c000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED1_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED1_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED1_SHIFT        14

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_6 :: ovr_fine_fall [13:12] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_FINE_FALL_MASK     0x00003000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_FINE_FALL_ALIGN    0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_FINE_FALL_BITS     2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_FINE_FALL_SHIFT    12

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_6 :: reserved2 [11:10] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED2_MASK         0x00000c00
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED2_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED2_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED2_SHIFT        10

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_6 :: ovr_fine_rise [09:08] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_FINE_RISE_MASK     0x00000300
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_FINE_RISE_ALIGN    0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_FINE_RISE_BITS     2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_FINE_RISE_SHIFT    8

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_6 :: reserved3 [07:06] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED3_MASK         0x000000c0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED3_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED3_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED3_SHIFT        6

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_6 :: ovr_step [05:00] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_STEP_MASK          0x0000003f
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_STEP_ALIGN         0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_STEP_BITS          6
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_STEP_SHIFT         0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_7
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_7 :: reserved0 [31:17] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED0_MASK         0xfffe0000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED0_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED0_BITS         15
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED0_SHIFT        17

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_7 :: ovr_en [16:16] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_EN_MASK            0x00010000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_EN_ALIGN           0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_EN_BITS            1
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_EN_SHIFT           16

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_7 :: reserved1 [15:14] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED1_MASK         0x0000c000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED1_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED1_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED1_SHIFT        14

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_7 :: ovr_fine_fall [13:12] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_FINE_FALL_MASK     0x00003000
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_FINE_FALL_ALIGN    0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_FINE_FALL_BITS     2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_FINE_FALL_SHIFT    12

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_7 :: reserved2 [11:10] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED2_MASK         0x00000c00
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED2_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED2_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED2_SHIFT        10

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_7 :: ovr_fine_rise [09:08] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_FINE_RISE_MASK     0x00000300
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_FINE_RISE_ALIGN    0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_FINE_RISE_BITS     2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_FINE_RISE_SHIFT    8

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_7 :: reserved3 [07:06] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED3_MASK         0x000000c0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED3_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED3_BITS         2
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED3_SHIFT        6

/* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_7 :: ovr_step [05:00] */
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_STEP_MASK          0x0000003f
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_STEP_ALIGN         0
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_STEP_BITS          6
#define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_STEP_SHIFT         0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE0 :: READ_CONTROL
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE0 :: READ_CONTROL :: reserved0 [31:10] */
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RESERVED0_MASK           0xfffffc00
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RESERVED0_ALIGN          0
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RESERVED0_BITS           22
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RESERVED0_SHIFT          10

/* DDR23_PHY_BYTE_LANE0 :: READ_CONTROL :: rd_data_dly [09:08] */
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_DATA_DLY_MASK         0x00000300
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_DATA_DLY_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_DATA_DLY_BITS         2
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_DATA_DLY_SHIFT        8

/* DDR23_PHY_BYTE_LANE0 :: READ_CONTROL :: reserved1 [07:04] */
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RESERVED1_MASK           0x000000f0
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RESERVED1_ALIGN          0
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RESERVED1_BITS           4
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RESERVED1_SHIFT          4

/* DDR23_PHY_BYTE_LANE0 :: READ_CONTROL :: dq_odt_enable [03:03] */
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_DQ_ODT_ENABLE_MASK       0x00000008
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_DQ_ODT_ENABLE_ALIGN      0
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_DQ_ODT_ENABLE_BITS       1
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_DQ_ODT_ENABLE_SHIFT      3

/* DDR23_PHY_BYTE_LANE0 :: READ_CONTROL :: dq_odt_adj [02:02] */
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_DQ_ODT_ADJ_MASK          0x00000004
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_DQ_ODT_ADJ_ALIGN         0
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_DQ_ODT_ADJ_BITS          1
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_DQ_ODT_ADJ_SHIFT         2

/* DDR23_PHY_BYTE_LANE0 :: READ_CONTROL :: rd_enb_odt_enable [01:01] */
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_ENB_ODT_ENABLE_MASK   0x00000002
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_ENB_ODT_ENABLE_ALIGN  0
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_ENB_ODT_ENABLE_BITS   1
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_ENB_ODT_ENABLE_SHIFT  1

/* DDR23_PHY_BYTE_LANE0 :: READ_CONTROL :: rd_enb_odt_adj [00:00] */
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_ENB_ODT_ADJ_MASK      0x00000001
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_ENB_ODT_ADJ_ALIGN     0
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_ENB_ODT_ADJ_BITS      1
#define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_ENB_ODT_ADJ_SHIFT     0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE0 :: READ_FIFO_STATUS
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE0 :: READ_FIFO_STATUS :: reserved0 [31:04] */
#define DDR23_PHY_BYTE_LANE0_READ_FIFO_STATUS_RESERVED0_MASK       0xfffffff0
#define DDR23_PHY_BYTE_LANE0_READ_FIFO_STATUS_RESERVED0_ALIGN      0
#define DDR23_PHY_BYTE_LANE0_READ_FIFO_STATUS_RESERVED0_BITS       28
#define DDR23_PHY_BYTE_LANE0_READ_FIFO_STATUS_RESERVED0_SHIFT      4

/* DDR23_PHY_BYTE_LANE0 :: READ_FIFO_STATUS :: status [03:00] */
#define DDR23_PHY_BYTE_LANE0_READ_FIFO_STATUS_STATUS_MASK          0x0000000f
#define DDR23_PHY_BYTE_LANE0_READ_FIFO_STATUS_STATUS_ALIGN         0
#define DDR23_PHY_BYTE_LANE0_READ_FIFO_STATUS_STATUS_BITS          4
#define DDR23_PHY_BYTE_LANE0_READ_FIFO_STATUS_STATUS_SHIFT         0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE0 :: READ_FIFO_CLEAR
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
#define DDR23_PHY_BYTE_LANE0_READ_FIFO_CLEAR_RESERVED0_MASK        0xfffffffe
#define DDR23_PHY_BYTE_LANE0_READ_FIFO_CLEAR_RESERVED0_ALIGN       0
#define DDR23_PHY_BYTE_LANE0_READ_FIFO_CLEAR_RESERVED0_BITS        31
#define DDR23_PHY_BYTE_LANE0_READ_FIFO_CLEAR_RESERVED0_SHIFT       1

/* DDR23_PHY_BYTE_LANE0 :: READ_FIFO_CLEAR :: clear [00:00] */
#define DDR23_PHY_BYTE_LANE0_READ_FIFO_CLEAR_CLEAR_MASK            0x00000001
#define DDR23_PHY_BYTE_LANE0_READ_FIFO_CLEAR_CLEAR_ALIGN           0
#define DDR23_PHY_BYTE_LANE0_READ_FIFO_CLEAR_CLEAR_BITS            1
#define DDR23_PHY_BYTE_LANE0_READ_FIFO_CLEAR_CLEAR_SHIFT           0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: idle [31:31] */
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_IDLE_MASK            0x80000000
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_IDLE_ALIGN           0
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_IDLE_BITS            1
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_IDLE_SHIFT           31

/* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_RESERVED0_MASK       0x7ff00000
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_RESERVED0_ALIGN      0
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_RESERVED0_BITS       11
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_RESERVED0_SHIFT      20

/* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dm_rxenb [19:19] */
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_RXENB_MASK        0x00080000
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_RXENB_ALIGN       0
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_RXENB_BITS        1
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_RXENB_SHIFT       19

/* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dm_iddq [18:18] */
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_IDDQ_MASK         0x00040000
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_IDDQ_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_IDDQ_BITS         1
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_IDDQ_SHIFT        18

/* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dm_reb [17:17] */
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_REB_MASK          0x00020000
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_REB_ALIGN         0
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_REB_BITS          1
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_REB_SHIFT         17

/* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dm_oeb [16:16] */
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_OEB_MASK          0x00010000
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_OEB_ALIGN         0
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_OEB_BITS          1
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_OEB_SHIFT         16

/* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dq_rxenb [15:15] */
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_RXENB_MASK        0x00008000
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_RXENB_ALIGN       0
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_RXENB_BITS        1
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_RXENB_SHIFT       15

/* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dq_iddq [14:14] */
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_IDDQ_MASK         0x00004000
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_IDDQ_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_IDDQ_BITS         1
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_IDDQ_SHIFT        14

/* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dq_reb [13:13] */
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_REB_MASK          0x00002000
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_REB_ALIGN         0
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_REB_BITS          1
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_REB_SHIFT         13

/* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dq_oeb [12:12] */
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_OEB_MASK          0x00001000
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_OEB_ALIGN         0
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_OEB_BITS          1
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_OEB_SHIFT         12

/* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: read_enb_rxenb [11:11] */
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_RXENB_MASK  0x00000800
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_RXENB_ALIGN 0
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_RXENB_BITS  1
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_RXENB_SHIFT 11

/* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: read_enb_iddq [10:10] */
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_IDDQ_MASK   0x00000400
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_IDDQ_ALIGN  0
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_IDDQ_BITS   1
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_IDDQ_SHIFT  10

/* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: read_enb_reb [09:09] */
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_REB_MASK    0x00000200
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_REB_ALIGN   0
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_REB_BITS    1
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_REB_SHIFT   9

/* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: read_enb_oeb [08:08] */
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_OEB_MASK    0x00000100
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_OEB_ALIGN   0
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_OEB_BITS    1
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_OEB_SHIFT   8

/* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dqs_rxenb [07:07] */
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_RXENB_MASK       0x00000080
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_RXENB_ALIGN      0
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_RXENB_BITS       1
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_RXENB_SHIFT      7

/* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dqs_iddq [06:06] */
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_IDDQ_MASK        0x00000040
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_IDDQ_ALIGN       0
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_IDDQ_BITS        1
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_IDDQ_SHIFT       6

/* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dqs_reb [05:05] */
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_REB_MASK         0x00000020
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_REB_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_REB_BITS         1
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_REB_SHIFT        5

/* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dqs_oeb [04:04] */
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_OEB_MASK         0x00000010
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_OEB_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_OEB_BITS         1
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_OEB_SHIFT        4

/* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: clk_rxenb [03:03] */
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_RXENB_MASK       0x00000008
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_RXENB_ALIGN      0
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_RXENB_BITS       1
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_RXENB_SHIFT      3

/* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: clk_iddq [02:02] */
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_IDDQ_MASK        0x00000004
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_IDDQ_ALIGN       0
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_IDDQ_BITS        1
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_IDDQ_SHIFT       2

/* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: clk_reb [01:01] */
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_REB_MASK         0x00000002
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_REB_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_REB_BITS         1
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_REB_SHIFT        1

/* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: clk_oeb [00:00] */
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_OEB_MASK         0x00000001
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_OEB_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_OEB_BITS         1
#define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_OEB_SHIFT        0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE0 :: DRIVE_PAD_CTL
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE0 :: DRIVE_PAD_CTL :: reserved0 [31:06] */
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RESERVED0_MASK          0xffffffc0
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RESERVED0_ALIGN         0
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RESERVED0_BITS          26
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RESERVED0_SHIFT         6

/* DDR23_PHY_BYTE_LANE0 :: DRIVE_PAD_CTL :: rt60b_ddr_read_enb [05:05] */
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RT60B_DDR_READ_ENB_MASK 0x00000020
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RT60B_DDR_READ_ENB_ALIGN 0
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RT60B_DDR_READ_ENB_BITS 1
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RT60B_DDR_READ_ENB_SHIFT 5

/* DDR23_PHY_BYTE_LANE0 :: DRIVE_PAD_CTL :: rt60b [04:04] */
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RT60B_MASK              0x00000010
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RT60B_ALIGN             0
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RT60B_BITS              1
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RT60B_SHIFT             4

/* DDR23_PHY_BYTE_LANE0 :: DRIVE_PAD_CTL :: sel_sstl18 [03:03] */
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SEL_SSTL18_MASK         0x00000008
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SEL_SSTL18_ALIGN        0
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SEL_SSTL18_BITS         1
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SEL_SSTL18_SHIFT        3

/* DDR23_PHY_BYTE_LANE0 :: DRIVE_PAD_CTL :: seltxdrv_ci [02:02] */
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SELTXDRV_CI_MASK        0x00000004
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SELTXDRV_CI_ALIGN       0
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SELTXDRV_CI_BITS        1
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SELTXDRV_CI_SHIFT       2

/* DDR23_PHY_BYTE_LANE0 :: DRIVE_PAD_CTL :: selrxdrv [01:01] */
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SELRXDRV_MASK           0x00000002
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SELRXDRV_ALIGN          0
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SELRXDRV_BITS           1
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SELRXDRV_SHIFT          1

/* DDR23_PHY_BYTE_LANE0 :: DRIVE_PAD_CTL :: slew [00:00] */
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SLEW_MASK               0x00000001
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SLEW_ALIGN              0
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SLEW_BITS               1
#define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SLEW_SHIFT              0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE0 :: CLOCK_PAD_DISABLE
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE0 :: CLOCK_PAD_DISABLE :: reserved0 [31:01] */
#define DDR23_PHY_BYTE_LANE0_CLOCK_PAD_DISABLE_RESERVED0_MASK      0xfffffffe
#define DDR23_PHY_BYTE_LANE0_CLOCK_PAD_DISABLE_RESERVED0_ALIGN     0
#define DDR23_PHY_BYTE_LANE0_CLOCK_PAD_DISABLE_RESERVED0_BITS      31
#define DDR23_PHY_BYTE_LANE0_CLOCK_PAD_DISABLE_RESERVED0_SHIFT     1

/* DDR23_PHY_BYTE_LANE0 :: CLOCK_PAD_DISABLE :: clk_pad_dis [00:00] */
#define DDR23_PHY_BYTE_LANE0_CLOCK_PAD_DISABLE_CLK_PAD_DIS_MASK    0x00000001
#define DDR23_PHY_BYTE_LANE0_CLOCK_PAD_DISABLE_CLK_PAD_DIS_ALIGN   0
#define DDR23_PHY_BYTE_LANE0_CLOCK_PAD_DISABLE_CLK_PAD_DIS_BITS    1
#define DDR23_PHY_BYTE_LANE0_CLOCK_PAD_DISABLE_CLK_PAD_DIS_SHIFT   0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE0 :: WR_PREAMBLE_MODE
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE0 :: WR_PREAMBLE_MODE :: reserved0 [31:01] */
#define DDR23_PHY_BYTE_LANE0_WR_PREAMBLE_MODE_RESERVED0_MASK       0xfffffffe
#define DDR23_PHY_BYTE_LANE0_WR_PREAMBLE_MODE_RESERVED0_ALIGN      0
#define DDR23_PHY_BYTE_LANE0_WR_PREAMBLE_MODE_RESERVED0_BITS       31
#define DDR23_PHY_BYTE_LANE0_WR_PREAMBLE_MODE_RESERVED0_SHIFT      1

/* DDR23_PHY_BYTE_LANE0 :: WR_PREAMBLE_MODE :: mode [00:00] */
#define DDR23_PHY_BYTE_LANE0_WR_PREAMBLE_MODE_MODE_MASK            0x00000001
#define DDR23_PHY_BYTE_LANE0_WR_PREAMBLE_MODE_MODE_ALIGN           0
#define DDR23_PHY_BYTE_LANE0_WR_PREAMBLE_MODE_MODE_BITS            1
#define DDR23_PHY_BYTE_LANE0_WR_PREAMBLE_MODE_MODE_SHIFT           0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE0 :: CLOCK_REG_CONTROL
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE0 :: CLOCK_REG_CONTROL :: reserved0 [31:02] */
#define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_RESERVED0_MASK      0xfffffffc
#define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_RESERVED0_ALIGN     0
#define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_RESERVED0_BITS      30
#define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_RESERVED0_SHIFT     2

/* DDR23_PHY_BYTE_LANE0 :: CLOCK_REG_CONTROL :: half_power [01:01] */
#define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_HALF_POWER_MASK     0x00000002
#define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_HALF_POWER_ALIGN    0
#define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_HALF_POWER_BITS     1
#define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_HALF_POWER_SHIFT    1

/* DDR23_PHY_BYTE_LANE0 :: CLOCK_REG_CONTROL :: pwrdn [00:00] */
#define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_PWRDN_MASK          0x00000001
#define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_PWRDN_ALIGN         0
#define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_PWRDN_BITS          1
#define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_PWRDN_SHIFT         0


/****************************************************************************
 * DDR23_PHY_DDR23_PHY_BYTE_LANE1
 ***************************************************************************/
/****************************************************************************
 * DDR23_PHY_BYTE_LANE1 :: REVISION
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE1 :: REVISION :: reserved0 [31:16] */
#define DDR23_PHY_BYTE_LANE1_REVISION_RESERVED0_MASK               0xffff0000
#define DDR23_PHY_BYTE_LANE1_REVISION_RESERVED0_ALIGN              0
#define DDR23_PHY_BYTE_LANE1_REVISION_RESERVED0_BITS               16
#define DDR23_PHY_BYTE_LANE1_REVISION_RESERVED0_SHIFT              16

/* DDR23_PHY_BYTE_LANE1 :: REVISION :: MAJOR [15:08] */
#define DDR23_PHY_BYTE_LANE1_REVISION_MAJOR_MASK                   0x0000ff00
#define DDR23_PHY_BYTE_LANE1_REVISION_MAJOR_ALIGN                  0
#define DDR23_PHY_BYTE_LANE1_REVISION_MAJOR_BITS                   8
#define DDR23_PHY_BYTE_LANE1_REVISION_MAJOR_SHIFT                  8

/* DDR23_PHY_BYTE_LANE1 :: REVISION :: MINOR [07:00] */
#define DDR23_PHY_BYTE_LANE1_REVISION_MINOR_MASK                   0x000000ff
#define DDR23_PHY_BYTE_LANE1_REVISION_MINOR_ALIGN                  0
#define DDR23_PHY_BYTE_LANE1_REVISION_MINOR_BITS                   8
#define DDR23_PHY_BYTE_LANE1_REVISION_MINOR_SHIFT                  0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE1 :: VDL_CALIBRATE
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE1 :: VDL_CALIBRATE :: reserved0 [31:05] */
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_RESERVED0_MASK          0xffffffe0
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_RESERVED0_ALIGN         0
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_RESERVED0_BITS          27
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_RESERVED0_SHIFT         5

/* DDR23_PHY_BYTE_LANE1 :: VDL_CALIBRATE :: calib_clocks [04:04] */
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_CLOCKS_MASK       0x00000010
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_CLOCKS_ALIGN      0
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_CLOCKS_BITS       1
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_CLOCKS_SHIFT      4

/* DDR23_PHY_BYTE_LANE1 :: VDL_CALIBRATE :: calib_test [03:03] */
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_TEST_MASK         0x00000008
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_TEST_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_TEST_BITS         1
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_TEST_SHIFT        3

/* DDR23_PHY_BYTE_LANE1 :: VDL_CALIBRATE :: calib_always [02:02] */
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_ALWAYS_MASK       0x00000004
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_ALWAYS_ALIGN      0
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_ALWAYS_BITS       1
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_ALWAYS_SHIFT      2

/* DDR23_PHY_BYTE_LANE1 :: VDL_CALIBRATE :: calib_once [01:01] */
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_ONCE_MASK         0x00000002
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_ONCE_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_ONCE_BITS         1
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_ONCE_SHIFT        1

/* DDR23_PHY_BYTE_LANE1 :: VDL_CALIBRATE :: calib_fast [00:00] */
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_FAST_MASK         0x00000001
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_FAST_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_FAST_BITS         1
#define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_FAST_SHIFT        0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE1 :: VDL_STATUS
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE1 :: VDL_STATUS :: reserved0 [31:14] */
#define DDR23_PHY_BYTE_LANE1_VDL_STATUS_RESERVED0_MASK             0xffffc000
#define DDR23_PHY_BYTE_LANE1_VDL_STATUS_RESERVED0_ALIGN            0
#define DDR23_PHY_BYTE_LANE1_VDL_STATUS_RESERVED0_BITS             18
#define DDR23_PHY_BYTE_LANE1_VDL_STATUS_RESERVED0_SHIFT            14

/* DDR23_PHY_BYTE_LANE1 :: VDL_STATUS :: calib_total [13:04] */
#define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_TOTAL_MASK           0x00003ff0
#define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_TOTAL_ALIGN          0
#define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_TOTAL_BITS           10
#define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_TOTAL_SHIFT          4

/* DDR23_PHY_BYTE_LANE1 :: VDL_STATUS :: reserved1 [03:02] */
#define DDR23_PHY_BYTE_LANE1_VDL_STATUS_RESERVED1_MASK             0x0000000c
#define DDR23_PHY_BYTE_LANE1_VDL_STATUS_RESERVED1_ALIGN            0
#define DDR23_PHY_BYTE_LANE1_VDL_STATUS_RESERVED1_BITS             2
#define DDR23_PHY_BYTE_LANE1_VDL_STATUS_RESERVED1_SHIFT            2

/* DDR23_PHY_BYTE_LANE1 :: VDL_STATUS :: calib_lock [01:01] */
#define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_LOCK_MASK            0x00000002
#define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_LOCK_ALIGN           0
#define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_LOCK_BITS            1
#define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_LOCK_SHIFT           1

/* DDR23_PHY_BYTE_LANE1 :: VDL_STATUS :: calib_idle [00:00] */
#define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_IDLE_MASK            0x00000001
#define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_IDLE_ALIGN           0
#define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_IDLE_BITS            1
#define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_IDLE_SHIFT           0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_0
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_0 :: reserved0 [31:17] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED0_MASK         0xfffe0000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED0_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED0_BITS         15
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED0_SHIFT        17

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_0 :: ovr_en [16:16] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_EN_MASK            0x00010000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_EN_ALIGN           0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_EN_BITS            1
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_EN_SHIFT           16

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_0 :: reserved1 [15:14] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED1_MASK         0x0000c000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED1_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED1_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED1_SHIFT        14

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_0 :: ovr_fine_fall [13:12] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_FINE_FALL_MASK     0x00003000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_FINE_FALL_ALIGN    0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_FINE_FALL_BITS     2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_FINE_FALL_SHIFT    12

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_0 :: reserved2 [11:10] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED2_MASK         0x00000c00
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED2_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED2_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED2_SHIFT        10

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_0 :: ovr_fine_rise [09:08] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_FINE_RISE_MASK     0x00000300
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_FINE_RISE_ALIGN    0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_FINE_RISE_BITS     2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_FINE_RISE_SHIFT    8

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_0 :: reserved3 [07:06] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED3_MASK         0x000000c0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED3_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED3_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED3_SHIFT        6

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_0 :: ovr_step [05:00] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_STEP_MASK          0x0000003f
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_STEP_ALIGN         0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_STEP_BITS          6
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_STEP_SHIFT         0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_1
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_1 :: reserved0 [31:17] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED0_MASK         0xfffe0000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED0_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED0_BITS         15
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED0_SHIFT        17

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_1 :: ovr_en [16:16] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_EN_MASK            0x00010000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_EN_ALIGN           0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_EN_BITS            1
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_EN_SHIFT           16

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_1 :: reserved1 [15:14] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED1_MASK         0x0000c000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED1_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED1_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED1_SHIFT        14

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_1 :: ovr_fine_fall [13:12] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_FINE_FALL_MASK     0x00003000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_FINE_FALL_ALIGN    0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_FINE_FALL_BITS     2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_FINE_FALL_SHIFT    12

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_1 :: reserved2 [11:10] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED2_MASK         0x00000c00
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED2_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED2_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED2_SHIFT        10

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_1 :: ovr_fine_rise [09:08] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_FINE_RISE_MASK     0x00000300
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_FINE_RISE_ALIGN    0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_FINE_RISE_BITS     2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_FINE_RISE_SHIFT    8

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_1 :: reserved3 [07:06] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED3_MASK         0x000000c0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED3_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED3_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED3_SHIFT        6

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_1 :: ovr_step [05:00] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_STEP_MASK          0x0000003f
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_STEP_ALIGN         0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_STEP_BITS          6
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_STEP_SHIFT         0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_2
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_2 :: reserved0 [31:17] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED0_MASK         0xfffe0000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED0_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED0_BITS         15
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED0_SHIFT        17

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_2 :: ovr_en [16:16] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_EN_MASK            0x00010000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_EN_ALIGN           0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_EN_BITS            1
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_EN_SHIFT           16

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_2 :: reserved1 [15:14] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED1_MASK         0x0000c000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED1_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED1_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED1_SHIFT        14

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_2 :: ovr_fine_fall [13:12] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_FINE_FALL_MASK     0x00003000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_FINE_FALL_ALIGN    0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_FINE_FALL_BITS     2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_FINE_FALL_SHIFT    12

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_2 :: reserved2 [11:10] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED2_MASK         0x00000c00
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED2_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED2_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED2_SHIFT        10

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_2 :: ovr_fine_rise [09:08] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_FINE_RISE_MASK     0x00000300
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_FINE_RISE_ALIGN    0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_FINE_RISE_BITS     2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_FINE_RISE_SHIFT    8

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_2 :: reserved3 [07:06] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED3_MASK         0x000000c0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED3_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED3_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED3_SHIFT        6

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_2 :: ovr_step [05:00] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_STEP_MASK          0x0000003f
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_STEP_ALIGN         0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_STEP_BITS          6
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_STEP_SHIFT         0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_3
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_3 :: reserved0 [31:17] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED0_MASK         0xfffe0000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED0_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED0_BITS         15
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED0_SHIFT        17

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_3 :: ovr_en [16:16] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_EN_MASK            0x00010000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_EN_ALIGN           0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_EN_BITS            1
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_EN_SHIFT           16

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_3 :: reserved1 [15:14] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED1_MASK         0x0000c000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED1_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED1_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED1_SHIFT        14

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_3 :: ovr_fine_fall [13:12] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_FINE_FALL_MASK     0x00003000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_FINE_FALL_ALIGN    0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_FINE_FALL_BITS     2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_FINE_FALL_SHIFT    12

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_3 :: reserved2 [11:10] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED2_MASK         0x00000c00
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED2_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED2_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED2_SHIFT        10

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_3 :: ovr_fine_rise [09:08] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_FINE_RISE_MASK     0x00000300
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_FINE_RISE_ALIGN    0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_FINE_RISE_BITS     2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_FINE_RISE_SHIFT    8

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_3 :: reserved3 [07:06] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED3_MASK         0x000000c0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED3_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED3_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED3_SHIFT        6

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_3 :: ovr_step [05:00] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_STEP_MASK          0x0000003f
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_STEP_ALIGN         0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_STEP_BITS          6
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_STEP_SHIFT         0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_4
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_4 :: reserved0 [31:17] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED0_MASK         0xfffe0000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED0_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED0_BITS         15
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED0_SHIFT        17

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_4 :: ovr_en [16:16] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_EN_MASK            0x00010000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_EN_ALIGN           0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_EN_BITS            1
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_EN_SHIFT           16

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_4 :: reserved1 [15:14] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED1_MASK         0x0000c000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED1_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED1_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED1_SHIFT        14

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_4 :: ovr_fine_fall [13:12] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_FINE_FALL_MASK     0x00003000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_FINE_FALL_ALIGN    0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_FINE_FALL_BITS     2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_FINE_FALL_SHIFT    12

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_4 :: reserved2 [11:10] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED2_MASK         0x00000c00
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED2_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED2_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED2_SHIFT        10

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_4 :: ovr_fine_rise [09:08] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_FINE_RISE_MASK     0x00000300
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_FINE_RISE_ALIGN    0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_FINE_RISE_BITS     2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_FINE_RISE_SHIFT    8

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_4 :: reserved3 [07:06] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED3_MASK         0x000000c0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED3_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED3_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED3_SHIFT        6

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_4 :: ovr_step [05:00] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_STEP_MASK          0x0000003f
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_STEP_ALIGN         0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_STEP_BITS          6
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_STEP_SHIFT         0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_5
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_5 :: reserved0 [31:17] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED0_MASK         0xfffe0000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED0_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED0_BITS         15
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED0_SHIFT        17

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_5 :: ovr_en [16:16] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_EN_MASK            0x00010000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_EN_ALIGN           0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_EN_BITS            1
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_EN_SHIFT           16

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_5 :: reserved1 [15:14] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED1_MASK         0x0000c000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED1_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED1_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED1_SHIFT        14

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_5 :: ovr_fine_fall [13:12] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_FINE_FALL_MASK     0x00003000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_FINE_FALL_ALIGN    0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_FINE_FALL_BITS     2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_FINE_FALL_SHIFT    12

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_5 :: reserved2 [11:10] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED2_MASK         0x00000c00
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED2_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED2_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED2_SHIFT        10

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_5 :: ovr_fine_rise [09:08] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_FINE_RISE_MASK     0x00000300
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_FINE_RISE_ALIGN    0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_FINE_RISE_BITS     2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_FINE_RISE_SHIFT    8

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_5 :: reserved3 [07:06] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED3_MASK         0x000000c0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED3_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED3_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED3_SHIFT        6

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_5 :: ovr_step [05:00] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_STEP_MASK          0x0000003f
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_STEP_ALIGN         0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_STEP_BITS          6
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_STEP_SHIFT         0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_6
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_6 :: reserved0 [31:17] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED0_MASK         0xfffe0000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED0_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED0_BITS         15
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED0_SHIFT        17

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_6 :: ovr_en [16:16] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_EN_MASK            0x00010000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_EN_ALIGN           0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_EN_BITS            1
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_EN_SHIFT           16

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_6 :: reserved1 [15:14] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED1_MASK         0x0000c000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED1_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED1_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED1_SHIFT        14

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_6 :: ovr_fine_fall [13:12] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_FINE_FALL_MASK     0x00003000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_FINE_FALL_ALIGN    0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_FINE_FALL_BITS     2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_FINE_FALL_SHIFT    12

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_6 :: reserved2 [11:10] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED2_MASK         0x00000c00
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED2_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED2_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED2_SHIFT        10

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_6 :: ovr_fine_rise [09:08] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_FINE_RISE_MASK     0x00000300
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_FINE_RISE_ALIGN    0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_FINE_RISE_BITS     2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_FINE_RISE_SHIFT    8

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_6 :: reserved3 [07:06] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED3_MASK         0x000000c0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED3_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED3_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED3_SHIFT        6

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_6 :: ovr_step [05:00] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_STEP_MASK          0x0000003f
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_STEP_ALIGN         0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_STEP_BITS          6
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_STEP_SHIFT         0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_7
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_7 :: reserved0 [31:17] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED0_MASK         0xfffe0000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED0_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED0_BITS         15
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED0_SHIFT        17

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_7 :: ovr_en [16:16] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_EN_MASK            0x00010000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_EN_ALIGN           0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_EN_BITS            1
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_EN_SHIFT           16

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_7 :: reserved1 [15:14] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED1_MASK         0x0000c000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED1_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED1_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED1_SHIFT        14

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_7 :: ovr_fine_fall [13:12] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_FINE_FALL_MASK     0x00003000
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_FINE_FALL_ALIGN    0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_FINE_FALL_BITS     2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_FINE_FALL_SHIFT    12

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_7 :: reserved2 [11:10] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED2_MASK         0x00000c00
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED2_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED2_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED2_SHIFT        10

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_7 :: ovr_fine_rise [09:08] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_FINE_RISE_MASK     0x00000300
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_FINE_RISE_ALIGN    0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_FINE_RISE_BITS     2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_FINE_RISE_SHIFT    8

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_7 :: reserved3 [07:06] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED3_MASK         0x000000c0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED3_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED3_BITS         2
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED3_SHIFT        6

/* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_7 :: ovr_step [05:00] */
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_STEP_MASK          0x0000003f
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_STEP_ALIGN         0
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_STEP_BITS          6
#define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_STEP_SHIFT         0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE1 :: READ_CONTROL
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE1 :: READ_CONTROL :: reserved0 [31:10] */
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RESERVED0_MASK           0xfffffc00
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RESERVED0_ALIGN          0
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RESERVED0_BITS           22
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RESERVED0_SHIFT          10

/* DDR23_PHY_BYTE_LANE1 :: READ_CONTROL :: rd_data_dly [09:08] */
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_DATA_DLY_MASK         0x00000300
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_DATA_DLY_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_DATA_DLY_BITS         2
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_DATA_DLY_SHIFT        8

/* DDR23_PHY_BYTE_LANE1 :: READ_CONTROL :: reserved1 [07:04] */
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RESERVED1_MASK           0x000000f0
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RESERVED1_ALIGN          0
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RESERVED1_BITS           4
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RESERVED1_SHIFT          4

/* DDR23_PHY_BYTE_LANE1 :: READ_CONTROL :: dq_odt_enable [03:03] */
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_DQ_ODT_ENABLE_MASK       0x00000008
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_DQ_ODT_ENABLE_ALIGN      0
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_DQ_ODT_ENABLE_BITS       1
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_DQ_ODT_ENABLE_SHIFT      3

/* DDR23_PHY_BYTE_LANE1 :: READ_CONTROL :: dq_odt_adj [02:02] */
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_DQ_ODT_ADJ_MASK          0x00000004
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_DQ_ODT_ADJ_ALIGN         0
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_DQ_ODT_ADJ_BITS          1
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_DQ_ODT_ADJ_SHIFT         2

/* DDR23_PHY_BYTE_LANE1 :: READ_CONTROL :: rd_enb_odt_enable [01:01] */
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_ENB_ODT_ENABLE_MASK   0x00000002
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_ENB_ODT_ENABLE_ALIGN  0
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_ENB_ODT_ENABLE_BITS   1
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_ENB_ODT_ENABLE_SHIFT  1

/* DDR23_PHY_BYTE_LANE1 :: READ_CONTROL :: rd_enb_odt_adj [00:00] */
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_ENB_ODT_ADJ_MASK      0x00000001
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_ENB_ODT_ADJ_ALIGN     0
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_ENB_ODT_ADJ_BITS      1
#define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_ENB_ODT_ADJ_SHIFT     0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE1 :: READ_FIFO_STATUS
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE1 :: READ_FIFO_STATUS :: reserved0 [31:04] */
#define DDR23_PHY_BYTE_LANE1_READ_FIFO_STATUS_RESERVED0_MASK       0xfffffff0
#define DDR23_PHY_BYTE_LANE1_READ_FIFO_STATUS_RESERVED0_ALIGN      0
#define DDR23_PHY_BYTE_LANE1_READ_FIFO_STATUS_RESERVED0_BITS       28
#define DDR23_PHY_BYTE_LANE1_READ_FIFO_STATUS_RESERVED0_SHIFT      4

/* DDR23_PHY_BYTE_LANE1 :: READ_FIFO_STATUS :: status [03:00] */
#define DDR23_PHY_BYTE_LANE1_READ_FIFO_STATUS_STATUS_MASK          0x0000000f
#define DDR23_PHY_BYTE_LANE1_READ_FIFO_STATUS_STATUS_ALIGN         0
#define DDR23_PHY_BYTE_LANE1_READ_FIFO_STATUS_STATUS_BITS          4
#define DDR23_PHY_BYTE_LANE1_READ_FIFO_STATUS_STATUS_SHIFT         0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE1 :: READ_FIFO_CLEAR
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE1 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
#define DDR23_PHY_BYTE_LANE1_READ_FIFO_CLEAR_RESERVED0_MASK        0xfffffffe
#define DDR23_PHY_BYTE_LANE1_READ_FIFO_CLEAR_RESERVED0_ALIGN       0
#define DDR23_PHY_BYTE_LANE1_READ_FIFO_CLEAR_RESERVED0_BITS        31
#define DDR23_PHY_BYTE_LANE1_READ_FIFO_CLEAR_RESERVED0_SHIFT       1

/* DDR23_PHY_BYTE_LANE1 :: READ_FIFO_CLEAR :: clear [00:00] */
#define DDR23_PHY_BYTE_LANE1_READ_FIFO_CLEAR_CLEAR_MASK            0x00000001
#define DDR23_PHY_BYTE_LANE1_READ_FIFO_CLEAR_CLEAR_ALIGN           0
#define DDR23_PHY_BYTE_LANE1_READ_FIFO_CLEAR_CLEAR_BITS            1
#define DDR23_PHY_BYTE_LANE1_READ_FIFO_CLEAR_CLEAR_SHIFT           0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: idle [31:31] */
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_IDLE_MASK            0x80000000
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_IDLE_ALIGN           0
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_IDLE_BITS            1
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_IDLE_SHIFT           31

/* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_RESERVED0_MASK       0x7ff00000
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_RESERVED0_ALIGN      0
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_RESERVED0_BITS       11
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_RESERVED0_SHIFT      20

/* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dm_rxenb [19:19] */
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_RXENB_MASK        0x00080000
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_RXENB_ALIGN       0
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_RXENB_BITS        1
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_RXENB_SHIFT       19

/* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dm_iddq [18:18] */
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_IDDQ_MASK         0x00040000
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_IDDQ_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_IDDQ_BITS         1
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_IDDQ_SHIFT        18

/* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dm_reb [17:17] */
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_REB_MASK          0x00020000
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_REB_ALIGN         0
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_REB_BITS          1
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_REB_SHIFT         17

/* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dm_oeb [16:16] */
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_OEB_MASK          0x00010000
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_OEB_ALIGN         0
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_OEB_BITS          1
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_OEB_SHIFT         16

/* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dq_rxenb [15:15] */
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_RXENB_MASK        0x00008000
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_RXENB_ALIGN       0
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_RXENB_BITS        1
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_RXENB_SHIFT       15

/* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dq_iddq [14:14] */
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_IDDQ_MASK         0x00004000
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_IDDQ_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_IDDQ_BITS         1
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_IDDQ_SHIFT        14

/* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dq_reb [13:13] */
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_REB_MASK          0x00002000
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_REB_ALIGN         0
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_REB_BITS          1
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_REB_SHIFT         13

/* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dq_oeb [12:12] */
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_OEB_MASK          0x00001000
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_OEB_ALIGN         0
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_OEB_BITS          1
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_OEB_SHIFT         12

/* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: read_enb_rxenb [11:11] */
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_RXENB_MASK  0x00000800
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_RXENB_ALIGN 0
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_RXENB_BITS  1
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_RXENB_SHIFT 11

/* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: read_enb_iddq [10:10] */
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_IDDQ_MASK   0x00000400
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_IDDQ_ALIGN  0
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_IDDQ_BITS   1
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_IDDQ_SHIFT  10

/* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: read_enb_reb [09:09] */
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_REB_MASK    0x00000200
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_REB_ALIGN   0
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_REB_BITS    1
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_REB_SHIFT   9

/* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: read_enb_oeb [08:08] */
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_OEB_MASK    0x00000100
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_OEB_ALIGN   0
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_OEB_BITS    1
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_OEB_SHIFT   8

/* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dqs_rxenb [07:07] */
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_RXENB_MASK       0x00000080
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_RXENB_ALIGN      0
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_RXENB_BITS       1
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_RXENB_SHIFT      7

/* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dqs_iddq [06:06] */
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_IDDQ_MASK        0x00000040
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_IDDQ_ALIGN       0
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_IDDQ_BITS        1
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_IDDQ_SHIFT       6

/* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dqs_reb [05:05] */
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_REB_MASK         0x00000020
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_REB_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_REB_BITS         1
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_REB_SHIFT        5

/* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dqs_oeb [04:04] */
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_OEB_MASK         0x00000010
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_OEB_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_OEB_BITS         1
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_OEB_SHIFT        4

/* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: clk_rxenb [03:03] */
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_RXENB_MASK       0x00000008
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_RXENB_ALIGN      0
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_RXENB_BITS       1
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_RXENB_SHIFT      3

/* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: clk_iddq [02:02] */
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_IDDQ_MASK        0x00000004
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_IDDQ_ALIGN       0
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_IDDQ_BITS        1
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_IDDQ_SHIFT       2

/* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: clk_reb [01:01] */
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_REB_MASK         0x00000002
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_REB_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_REB_BITS         1
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_REB_SHIFT        1

/* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: clk_oeb [00:00] */
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_OEB_MASK         0x00000001
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_OEB_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_OEB_BITS         1
#define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_OEB_SHIFT        0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE1 :: DRIVE_PAD_CTL
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE1 :: DRIVE_PAD_CTL :: reserved0 [31:06] */
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RESERVED0_MASK          0xffffffc0
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RESERVED0_ALIGN         0
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RESERVED0_BITS          26
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RESERVED0_SHIFT         6

/* DDR23_PHY_BYTE_LANE1 :: DRIVE_PAD_CTL :: rt60b_ddr_read_enb [05:05] */
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RT60B_DDR_READ_ENB_MASK 0x00000020
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RT60B_DDR_READ_ENB_ALIGN 0
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RT60B_DDR_READ_ENB_BITS 1
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RT60B_DDR_READ_ENB_SHIFT 5

/* DDR23_PHY_BYTE_LANE1 :: DRIVE_PAD_CTL :: rt60b [04:04] */
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RT60B_MASK              0x00000010
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RT60B_ALIGN             0
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RT60B_BITS              1
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RT60B_SHIFT             4

/* DDR23_PHY_BYTE_LANE1 :: DRIVE_PAD_CTL :: sel_sstl18 [03:03] */
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SEL_SSTL18_MASK         0x00000008
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SEL_SSTL18_ALIGN        0
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SEL_SSTL18_BITS         1
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SEL_SSTL18_SHIFT        3

/* DDR23_PHY_BYTE_LANE1 :: DRIVE_PAD_CTL :: seltxdrv_ci [02:02] */
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SELTXDRV_CI_MASK        0x00000004
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SELTXDRV_CI_ALIGN       0
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SELTXDRV_CI_BITS        1
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SELTXDRV_CI_SHIFT       2

/* DDR23_PHY_BYTE_LANE1 :: DRIVE_PAD_CTL :: selrxdrv [01:01] */
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SELRXDRV_MASK           0x00000002
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SELRXDRV_ALIGN          0
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SELRXDRV_BITS           1
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SELRXDRV_SHIFT          1

/* DDR23_PHY_BYTE_LANE1 :: DRIVE_PAD_CTL :: slew [00:00] */
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SLEW_MASK               0x00000001
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SLEW_ALIGN              0
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SLEW_BITS               1
#define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SLEW_SHIFT              0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE1 :: CLOCK_PAD_DISABLE
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE1 :: CLOCK_PAD_DISABLE :: reserved0 [31:01] */
#define DDR23_PHY_BYTE_LANE1_CLOCK_PAD_DISABLE_RESERVED0_MASK      0xfffffffe
#define DDR23_PHY_BYTE_LANE1_CLOCK_PAD_DISABLE_RESERVED0_ALIGN     0
#define DDR23_PHY_BYTE_LANE1_CLOCK_PAD_DISABLE_RESERVED0_BITS      31
#define DDR23_PHY_BYTE_LANE1_CLOCK_PAD_DISABLE_RESERVED0_SHIFT     1

/* DDR23_PHY_BYTE_LANE1 :: CLOCK_PAD_DISABLE :: clk_pad_dis [00:00] */
#define DDR23_PHY_BYTE_LANE1_CLOCK_PAD_DISABLE_CLK_PAD_DIS_MASK    0x00000001
#define DDR23_PHY_BYTE_LANE1_CLOCK_PAD_DISABLE_CLK_PAD_DIS_ALIGN   0
#define DDR23_PHY_BYTE_LANE1_CLOCK_PAD_DISABLE_CLK_PAD_DIS_BITS    1
#define DDR23_PHY_BYTE_LANE1_CLOCK_PAD_DISABLE_CLK_PAD_DIS_SHIFT   0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE1 :: WR_PREAMBLE_MODE
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE1 :: WR_PREAMBLE_MODE :: reserved0 [31:01] */
#define DDR23_PHY_BYTE_LANE1_WR_PREAMBLE_MODE_RESERVED0_MASK       0xfffffffe
#define DDR23_PHY_BYTE_LANE1_WR_PREAMBLE_MODE_RESERVED0_ALIGN      0
#define DDR23_PHY_BYTE_LANE1_WR_PREAMBLE_MODE_RESERVED0_BITS       31
#define DDR23_PHY_BYTE_LANE1_WR_PREAMBLE_MODE_RESERVED0_SHIFT      1

/* DDR23_PHY_BYTE_LANE1 :: WR_PREAMBLE_MODE :: mode [00:00] */
#define DDR23_PHY_BYTE_LANE1_WR_PREAMBLE_MODE_MODE_MASK            0x00000001
#define DDR23_PHY_BYTE_LANE1_WR_PREAMBLE_MODE_MODE_ALIGN           0
#define DDR23_PHY_BYTE_LANE1_WR_PREAMBLE_MODE_MODE_BITS            1
#define DDR23_PHY_BYTE_LANE1_WR_PREAMBLE_MODE_MODE_SHIFT           0


/****************************************************************************
 * DDR23_PHY_BYTE_LANE1 :: CLOCK_REG_CONTROL
 ***************************************************************************/
/* DDR23_PHY_BYTE_LANE1 :: CLOCK_REG_CONTROL :: reserved0 [31:02] */
#define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_RESERVED0_MASK      0xfffffffc
#define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_RESERVED0_ALIGN     0
#define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_RESERVED0_BITS      30
#define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_RESERVED0_SHIFT     2

/* DDR23_PHY_BYTE_LANE1 :: CLOCK_REG_CONTROL :: half_power [01:01] */
#define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_HALF_POWER_MASK     0x00000002
#define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_HALF_POWER_ALIGN    0
#define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_HALF_POWER_BITS     1
#define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_HALF_POWER_SHIFT    1

/* DDR23_PHY_BYTE_LANE1 :: CLOCK_REG_CONTROL :: pwrdn [00:00] */
#define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_PWRDN_MASK          0x00000001
#define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_PWRDN_ALIGN         0
#define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_PWRDN_BITS          1
#define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_PWRDN_SHIFT         0


/****************************************************************************
 * Datatype Definitions.
 ***************************************************************************/
#endif /* #ifndef DDR23_H__ */

/* End of File */
